// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: fbdimm.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// ========== Copyright Header End ============================================
module fbdimm ( ps , ps_bar, sn , sn_bar, pn, pn_bar, ss , ss_bar , // channel interface
sclk,dq,err_en,dram_clk,dram_2x_clk, link_clk,ref_2x_clk,clk_int,clk_int_2x);
module fbdimm ( ps , ps_bar, sn , sn_bar, pn, pn_bar, ss , ss_bar , // channel interface
sclk,reset_n,err_en, dram_clk,dram_2x_clk, link_clk,ref_2x_clk,clk_int,clk_int_2x);
output [NB_LINK-1:0] pn,pn_bar; // primary northbound
input [NB_LINK-1:0] sn,sn_bar; // secondary northbound
output [SB_LINK-1:0] ss,ss_bar; // secondary southbound
input [SB_LINK-1:0] ps,ps_bar; // primary southbound
input dram_clk,dram_2x_clk, link_clk,ref_2x_clk,clk_int,clk_int_2x;
wire [71:0] data_in,data_out;
wire get_wbuffer_data,put_rbuffer_data;
wire [31:0] dcalcsr,dcaladdr,drc;
wire dram_clk,dram_2x_clk,link_clk,ref_2x_clk,clk_int,clk_int_2x;
wire [18:0] cke_rank0,cke_rank1,bcs,bras,bcas,bwe,dqs,bdqs,dm_rdqs,brdqs,odt,areset,term;
wire dram_cmd_vld_delayed,cke_reg_delayed;
amb_top #(NB_LINK,SB_LINK,DS) amb( .ps ( ps ),
.link_clk_bar (~link_clk),
.frm_boundary ( frm_boundary),
.command_in ( command_in),
.command_rdy ( command_rdy),
.command_type ( command_type),
.get_wbuffer_data ( get_wbuffer_data),
.put_rbuffer_data ( put_rbuffer_data),
.clear_dcalcsr31 ( clear_dcalcsr31 ),
.dram_2x_clk ( dram_2x_clk),
.ref_2x_clk ( ref_2x_clk),
.ddrio_nbencode_rd ( ddrio_nbencode_rd ),
.dram_cmd_vld_delayed ( dram_cmd_vld_delayed),
.sb_crc_error ( sb_crc_error),
.cke_reg_delayed ( cke_reg_delayed)
amb_top #(NB_LINK,SB_LINK,DS) amb( .ps ( ps ),
.link_clk_bar (~link_clk),
.frm_boundary ( frm_boundary),
.command_in ( command_in),
.command_type ( command_type),
.command_rdy ( command_rdy),
.get_wbuffer_data ( get_wbuffer_data),
.put_rbuffer_data ( put_rbuffer_data),
.clear_dcalcsr31 ( clear_dcalcsr31 ),
.ddrio_nbencode_rd ( ddrio_nbencode_rd ),
.ref_2x_clk ( ref_2x_clk),
.dram_cmd_vld_delayed ( dram_cmd_vld_delayed),
.sb_crc_error ( sb_crc_error),
.cke_reg_delayed ( cke_reg_delayed),
.dram_2x_clk ( dram_2x_clk)
`ifdef FBDIMM_EXTERNAL_CLK_GEN
fbdimm_clk_gen fbdimm_clk_gen (.sclk ( sclk),
.frm_boundary_sb ( frm_boundary),
.dram_2x_clk ( dram_2x_clk),
.clk_int_2x ( clk_int_2x),
.ref_2x_clk ( ref_2x_clk));
`ifdef AXIS_FBDIMM_NO_FSR
.dram_2x_clk ( dram_2x_clk),
.command_in ( command_in),
.command_type ( command_type),
.ddrio_nbencode_rd ( ddrio_nbencode_rd ),
.command_rdy ( command_rdy ),
.get_wbuffer_data ( get_wbuffer_data),
.put_rbuffer_data ( put_rbuffer_data),
.frm_boundary ( frm_boundary),
.clear_dcalcsr31 ( clear_dcalcsr31),
.drams_on_out ( drams_on),
.sb_crc_error ( sb_crc_error),
`ifdef AXIS_FBDIMM_NO_FSR
.dram_2x_clk ( dram_2x_clk),
.command_in ( command_in),
.command_type ( command_type ),
.command_rdy ( command_rdy ),
.get_wbuffer_data ( get_wbuffer_data),
.put_rbuffer_data ( put_rbuffer_data),
.frm_boundary ( frm_boundary),
.clear_dcalcsr31 ( clear_dcalcsr31),
.ddrio_nbencode_rd ( ddrio_nbencode_rd ),
.drams_on_out ( drams_on),
.sb_crc_error ( sb_crc_error),
// Dram devices for X4 configuration
`ifdef ZEROIN_DDR2_DRAM_MONITOR_X
zi_cw_ddr2_sdram_2_0_monitor #( 1, /* Constraints mode */
15, /* ROW_ADDRESS_WIDTH */
1, /* DLL_TRACKING_ENABLE */
12, /* AUTOPRECHARGE_ENABLE_ADDRESS_BIT */
1, /* READ_BEFORE_WRITE_CHECK_ENABLE */
3, /* BANK_ADDRESS_WITDH */
1, /* ENABLE_PRECHARGE_TO_IDLE_BANK */
ZeroIn_DDR2_MON ( .ck (dram_clk),
assign cs_sel = cs_sel_reg;
if ( $test$plusargs("fbdimm0_disable") && ( DS == 0 ) )
cs_sel_reg = 8'b11111110;
if ( $test$plusargs("fbdimm1_disable") && ( DS == 1 ) )
cs_sel_reg = 8'b11111101;
if ( $test$plusargs("fbdimm2_disable") && ( DS == 2 ) )
cs_sel_reg = 8'b11111011;
if ( $test$plusargs("fbdimm3_disable") && ( DS == 3 ) )
cs_sel_reg = 8'b11110111;
if ( $test$plusargs("fbdimm4_disable") && ( DS == 4 ) )
cs_sel_reg = 8'b11101111;
if ( $test$plusargs("fbdimm5_disable") && ( DS == 5 ) )
cs_sel_reg = 8'b11011111;
if ( $test$plusargs("fbdimm6_disable") && ( DS == 6 ) )
cs_sel_reg = 8'b10111111;
if ( $test$plusargs("fbdimm7_disable") && ( DS == 7 ) )
cs_sel_reg = 8'b01111111;
cs_sel_reg = 8'b00000000;
fbdimm_DIMMx8 fbdimm_DIMMx8
fbdimm_DIMMx4 fbdimm_DIMMx4
.bCS (bcs[18:1] | (!drams_on ? bcs[18:1] : {18{rs}}) ),
wire dram_mon_areset = dram_areset;
always@(posedge dram_clk)
ddr2_monitor #( 2, /* tMRD */
0, /* ADDITIVE LATENCY */
2 /* DATA_STROBE_NUM */ )
.areset (dram_mon_areset),
.cs_bar (cs_sel | {8{rs}} ),
`ifdef DRAM_SAT // to be removed later
amb_dram_err_inject amb_dram_err_inj (.clk (dram_clk),
.DRAM_CS_L (cs_sel[7:0]),
.CHNL_ERR_ENABLE (err_en),
.AMB_L0_STATE (~amb.init));
fbdimm_DIMMx8 fbdimm_DIMMx8_rank2
fbdimm_DIMMx4 fbdimm_DIMMx4_rank2
.bCS (bcs[18:1] | (!drams_on ? bcs[18:1] : {18{~rs}}) ),
`endif // AXIS_DDR2_MODEL
fbdimm_tasks fbdimm_tasks();
// Initialization and reset sequence
`endif // !AXIS_FBDIMM_HW