// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: idle_lfsr.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
input frm_begin,frm_boundary;
output [13:0] pn0_out,pn1_out,pn2_out,pn3_out,pn4_out,pn5_out;
output [13:0] pn11_out,pn10_out,pn9_out,pn8_out,pn7_out,pn6_out;
// internal registers/wires
assign lfsr_clk = next_idle_state;
assign reset_ff=(reset_cnt != 0);
Xo_tmp = 12'b000000000001;
assign Xo_tmp12 = next_idle_state ? Xo_tmp[0] : ~Xo_tmp[0];
assign pn0_out = (start_lfsr & ~reset_ff) ? {Xo_tmp[0],Xo_tmp12,Xo_tmp[11:0]} : 1'b0 ;
assign pn1_out = (start_lfsr & ~reset_ff) ? {Xo_tmp[0],Xo_tmp12,Xo_tmp[11:0]} : 1'b0 ;
assign pn2_out = (start_lfsr & ~reset_ff) ? {Xo_tmp[0],Xo_tmp12,Xo_tmp[11:0]} : 1'b0 ;
assign pn3_out = (start_lfsr & ~reset_ff) ? {Xo_tmp[0],Xo_tmp12,Xo_tmp[11:0]} : 1'b0 ;
assign pn4_out = (start_lfsr & ~reset_ff) ? {Xo_tmp[0],Xo_tmp12,Xo_tmp[11:0]} : 1'b0 ;
assign pn5_out = (start_lfsr & ~reset_ff) ? {Xo_tmp[0],Xo_tmp12,Xo_tmp[11:0]} : 1'b0 ;
assign pn6_out = (start_lfsr & ~reset_ff) ? {Xo_tmp[0],~Xo_tmp12,Xo_tmp[11:0]} : 1'b0 ;
assign pn7_out = (start_lfsr & ~reset_ff) ? {Xo_tmp[0],~Xo_tmp12,Xo_tmp[11:0]} : 1'b0 ;
assign pn8_out = (start_lfsr & ~reset_ff) ? {Xo_tmp[0],~Xo_tmp12,Xo_tmp[11:0]} : 1'b0 ;
assign pn9_out = (start_lfsr & ~reset_ff) ? {Xo_tmp[0],~Xo_tmp12,Xo_tmp[11:0]} : 1'b0 ;
assign pn10_out = (start_lfsr & ~reset_ff) ? {Xo_tmp[0],~Xo_tmp12,Xo_tmp[11:0]} : 1'b0 ;
assign pn11_out = (start_lfsr & ~reset_ff) ? {Xo_tmp[0],~Xo_tmp12,Xo_tmp[11:0]} : 1'b0 ;
shifter_p #(1) shft_start_lfsr (.signal_in (start_lfsr),
.signal_out (start_lfsr_d),
always@(posedge frm_boundary) if ( start_lfsr )
reset_cnt <= 9 + drc[7:4] + drc[3:0];
always @(posedge frm_boundary) if ( start_lfsr )
Xo[11] <= Xo[0] ^ Xo[3] ^ Xo[4] ^ Xo[7];
Xo_tmp[11] <= Xo_tmp[0] ^ Xo_tmp[3] ^ Xo_tmp[4] ^ Xo_tmp[7];
Xo_tmp[10] <= Xo_tmp[11];
module idle_lfsr (reset, frm_begin, dtm_reset, lfsr_output, clk, frm_boundary, electrical_idle);
output [13:0] lfsr_output;
// internal registers/wires
wire reset_ff=(reset_cnt != 0);
assign Xo_tmp12 = next_idle_state ? Xo_tmp[0] : ~Xo_tmp[0];
always@(negedge frm_boundary)
if ( start_lfsr & ~reset_ff )
enable_lfsr_output <= 1'b1;
enable_lfsr_output <= 1'b0;
assign lfsr_output[13:0]= (enable_lfsr_output) ? {Xo_tmp[0],Xo_tmp12,Xo_tmp[11:0]} : 1'b0 ;
assign lfsr_output[13:0]= (start_lfsr & ~reset_ff) ? {Xo_tmp[0],Xo_tmp12,Xo_tmp[11:0]} : 1'b0 ;
assign lfsr_clk = next_idle_state;
always@(posedge frm_boundary) if ( start_lfsr | electrical_idle )
reset_cnt <= reset_cnt - 1;
always @(posedge lfsr_clk) begin
Xo_tmp<=12'b000000000001;
Xo_tmp[11:0] <= Xo[11:0];
always@(negedge frm_begin)
start_lfsr_d7 <= start_lfsr;
always@(negedge frm_boundary)
start_lfsr_d7 <= start_lfsr;
shifter_p #(1) shft (.signal_in ( start_lfsr ),
.signal_out (start_lfsr_d7),
always@(posedge clk) if ( start_lfsr_d7 | electrical_idle )
4'h0: begin curr_state <= 4'h1; end
4'h1: begin curr_state <= 4'h2; end
4'h2: begin curr_state <= 4'h3; end
4'h3: begin curr_state <= 4'h4; end
4'h4: begin curr_state <= 4'h5; end
4'h5: begin curr_state <= 4'h6; next_idle_state <= ~next_idle_state; end
4'h6: begin curr_state <= 4'h7; end
4'h7: begin curr_state <= 4'h8; end
4'h8: begin curr_state <= 4'h9; end
4'h9: begin curr_state <= 4'ha; end
4'ha: begin curr_state <= 4'hb; end
4'hb: begin curr_state <= 4'h0; next_idle_state <= ~next_idle_state; end
always @(posedge lfsr_clk) begin
Xo[11] <= Xo[0] ^ Xo[3] ^ Xo[4] ^ Xo[7];
module chmon_idle_lfsr(reset,
input frm_begin,frm_boundary;
input [13:0] pn_prev_in,pn_curr_in;
// internal registers/wires
wire [13:0] Xo, pn_prev_in_map,pn_curr_in_map;
wire reset_ff=(reset_cnt != 0);
assign alert_frame = alert_frame_reg;
assign pn_prev_in_map = (( nb_config == 4'b1111 )) ? pn_prev_in : // All lanes are good
(( nb_config == 4'b1101 )) ? {pn_prev_in[13:0]} : // map nb13
(( nb_config == 4'b1100 )) ? {pn_prev_in[13] ,pn_prev_in[11:0]} : // map nb12
(( nb_config == 4'b1011 )) ? {pn_prev_in[13:12],pn_prev_in[10:0]} : // map nb11
(( nb_config == 4'b1010 )) ? {pn_prev_in[13:11],pn_prev_in[09:0]} : // map nb10
(( nb_config == 4'b1001 )) ? {pn_prev_in[13:10],pn_prev_in[08:0]} : // map nb9
(( nb_config == 4'b1000 )) ? {pn_prev_in[13:09],pn_prev_in[07:0]} : // map nb8
(( nb_config == 4'b0111 )) ? {pn_prev_in[13:08],pn_prev_in[06:0]} : // map nb7
(( nb_config == 4'b0110 )) ? {pn_prev_in[13:07],pn_prev_in[05:0]} : // map nb6
(( nb_config == 4'b0101 )) ? {pn_prev_in[13:06],pn_prev_in[04:0]} : // map nb5
(( nb_config == 4'b0100 )) ? {pn_prev_in[13:05],pn_prev_in[03:0]} : // map nb4
(( nb_config == 4'b0011 )) ? {pn_prev_in[13:04],pn_prev_in[02:0]} : // map nb3
(( nb_config == 4'b0010 )) ? {pn_prev_in[13:03],pn_prev_in[01:0]} : // map nb2
(( nb_config == 4'b0001 )) ? {pn_prev_in[13:02],pn_prev_in[0] } : // map nb1
(( nb_config == 4'b0000 )) ? {pn_prev_in[13:01]} : pn_prev_in; // map nb0
assign pn_curr_in_map = (( nb_config == 4'b1111 )) ? pn_curr_in : // All lanes are good
(( nb_config == 4'b1101 )) ? {pn_curr_in[13:0]} : // map nb13
(( nb_config == 4'b1100 )) ? {pn_curr_in[13] ,pn_curr_in[11:0]} : // map nb12
(( nb_config == 4'b1011 )) ? {pn_curr_in[13:12],pn_curr_in[10:0]} : // map nb11
(( nb_config == 4'b1010 )) ? {pn_curr_in[13:11],pn_curr_in[09:0]} : // map nb10
(( nb_config == 4'b1001 )) ? {pn_curr_in[13:10],pn_curr_in[08:0]} : // map nb9
(( nb_config == 4'b1000 )) ? {pn_curr_in[13:09],pn_curr_in[07:0]} : // map nb8
(( nb_config == 4'b0111 )) ? {pn_curr_in[13:08],pn_curr_in[06:0]} : // map nb7
(( nb_config == 4'b0110 )) ? {pn_curr_in[13:07],pn_curr_in[05:0]} : // map nb6
(( nb_config == 4'b0101 )) ? {pn_curr_in[13:06],pn_curr_in[04:0]} : // map nb5
(( nb_config == 4'b0100 )) ? {pn_curr_in[13:05],pn_curr_in[03:0]} : // map nb4
(( nb_config == 4'b0011 )) ? {pn_curr_in[13:04],pn_curr_in[02:0]} : // map nb3
(( nb_config == 4'b0010 )) ? {pn_curr_in[13:03],pn_curr_in[01:0]} : // map nb2
(( nb_config == 4'b0001 )) ? {pn_curr_in[13:02],pn_curr_in[0] } : // map nb1
(( nb_config == 4'b0000 )) ? {pn_curr_in[13:01]} : pn_curr_in; // map nb0
always@(negedge frm_boundary)
if ( ( pn_curr_in_map !== 14'h0 ) && ( pn_prev_in_map !== 14'h0 ) )
( pn_curr_in_map[0] == pn_prev_in_map[01] ) &&
( pn_curr_in_map[1] == pn_prev_in_map[02] ) &&
( pn_curr_in_map[2] == pn_prev_in_map[03] ) &&
( pn_curr_in_map[3] == pn_prev_in_map[04] ) &&
( pn_curr_in_map[4] == pn_prev_in_map[05] ) &&
( pn_curr_in_map[5] == pn_prev_in_map[06] ) &&
( pn_curr_in_map[6] == pn_prev_in_map[07] ) &&
( pn_curr_in_map[7] == pn_prev_in_map[08] ) &&
( pn_curr_in_map[8] == pn_prev_in_map[09] ) &&
( pn_curr_in_map[9] == pn_prev_in_map[10] ) &&
( pn_curr_in_map[10] == pn_prev_in_map[11] ) &&
( pn_curr_in_map[11] == ( pn_prev_in_map[00] ^ pn_prev_in_map[3] ^ pn_prev_in_map[4] ^ pn_prev_in_map[7]) ) )
// this is an expected idle frame
end // if ( ( pn_curr_in !== 14'h0 ) && ( pn_prev_in !== 14'h0 ) )
end // (~reset & is_idle )