verif/model/verilog/mem/fbdimm/design/send_ts0.v

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//
// OpenSPARC T2 Processor File: send_ts0.v
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module send_ts0(start,data,input_bit,serial_bit,link_clk);


input start;
input [143:0] data;
input link_clk;
output serial_bit;
input input_bit;

reg bit_reg;
reg enable_serial_bit;
reg [143:0] data_reg;

assign serial_bit= start ? input_bit : 1'b0;

/*
initial begin
enable_serial_bit=0;
end


always@(posedge link_clk)
begin
 if ( start ) begin
   enable_serial_bit=1;
   data_reg = data;
 end

 if ( (start || enable_serial_bit) && ( data[143:0] !== 144'h0) )
 begin
   bit_reg=data_reg[143];
   data_reg[143:0]={data_reg[142:0],1'b0};
 end

  if ( data[143:0] == 144'h0)
   enable_serial_bit=0;

end
*/

endmodule