design/fpga/rtl/fpga_rtl.flist

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: fpga_rtl.flist
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
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// ========== Copyright Header End ============================================
+define+TOP=t2_fpga
+define+INITLATZERO
+define+FPGA_SIM
+define+LIB
+define+FPGA
+define+FPGA_MONITOR
+incdir+$DV_ROOT/design/fpga/rtl
$DV_ROOT/design/fpga/opencores/timescale.v
$DV_ROOT/design/fpga/opencores/uart_receiver.v
$DV_ROOT/design/fpga/opencores/uart_regs.v
$DV_ROOT/design/fpga/opencores/uart_rfifo.v
$DV_ROOT/design/fpga/opencores/uart_sync_flops.v
$DV_ROOT/design/fpga/opencores/uart_tfifo.v
$DV_ROOT/design/fpga/opencores/uart_top.v
$DV_ROOT/design/fpga/opencores/uart_transmitter.v
$DV_ROOT/design/fpga/opencores/uart_wb.v
$DV_ROOT/design/fpga/opencores/spc2wbm.v
$DV_ROOT/design/fpga/opencores/mem_harness.v
$DV_ROOT/design/fpga/opencores/raminfr.v
$DV_ROOT/design/fpga/rtl/t2_fpga.v
$DV_ROOT/design/fpga/rtl/l2_dir.v
$DV_ROOT/design/fpga/rtl/t2.v
$DV_ROOT/design/sys/iop/spc/rtl/spc.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu.v
$DV_ROOT/design/sys/iop/spc/rtl/spc_msf0_dp.v
$DV_ROOT/design/sys/iop/spc/rtl/spc_msf1_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/ccx.v
$DV_ROOT/libs/clk/rtl/clkgen_ccx_cmp.v
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_ccx_cmp_cust/rtl/n2_clk_ccx_cmp_cust.v
$DV_ROOT/design/sys/iop/ccx/rtl/cpx.v
$DV_ROOT/design/sys/iop/ccx/rtl/pcx.v
$DV_ROOT/design/sys/iop/ccx/rtl/ccx_trep.v
$DV_ROOT/design/sys/iop/ccx/rtl/ccx_tstg.v
$DV_ROOT/libs/clk/rtl/clkgen_spc_cmp.v
$DV_ROOT/design/sys/iop/spc/dec/rtl/dec.v
$DV_ROOT/design/sys/iop/spc/dec/rtl/dec_dcd_ctl.v
$DV_ROOT/design/sys/iop/spc/dec/rtl/dec_del_ctl.v
$DV_ROOT/design/sys/iop/l2t/rtl/l2t_dmo_dp.v
$DV_ROOT/design/sys/iop/spc/exu/rtl/exu.v
$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu.v
$DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_cmt_ctl.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_agc_ctl.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ibu.v
$DV_ROOT/design/sys/iop/spc/rtl/spc_lb_ctl.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu.v
$DV_ROOT/design/sys/iop/spc/rtl/spc_mb0_ctl.v
$DV_ROOT/design/sys/iop/spc/rtl/spc_mb1_ctl.v
$DV_ROOT/design/sys/iop/spc/rtl/spc_mb2_ctl.v
$DV_ROOT/design/sys/iop/spc/exu/rtl/exu_mdp_dp.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu.v
$DV_ROOT/design/sys/iop/spc/pku/rtl/pku.v
$DV_ROOT/design/sys/iop/spc/pmu/rtl/pmu.v
$DV_ROOT/design/sys/iop/spc/rtl/spc_rep1_dp.v
$DV_ROOT/design/sys/iop/spc/spu/rtl/spu.v
$DV_ROOT/design/sys/iop/spc/rtl/dmo_dp.v
$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpc_ctl.v
$DV_ROOT/design/sys/iop/l2t/rtl/l2t_vuad_ctl.v
$DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_ipc_ctl.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_htc_ctl.v
$DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_ipd_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/pcx_mar_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/pcx_mal_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/pcx_mbl_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/pcx_mcr_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/pcx_bfd_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/pcx_ob1_dp.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_lsi_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_msb_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_agd_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_byp_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_ctx_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_err_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_itd_dp.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ibu_ibf_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/ccx_ard_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/cpx_bfd_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/cpx_bfg_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/cpx_mal_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/cpx_mbl_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/cpx_mbr_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/cpx_mcl_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/cpx_mcr_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/cpx_ob1_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/cpx_ob2_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/cpx_rep_dp.v
$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fad_dp.v
$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fdd_dp.v
$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fgd_dp.v
$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpe_dp.v
$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpf_dp.v
$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpy_dp.v
$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_rep_dp.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_ard_dp.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_asd_dp.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_cid_dp.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcd_dp.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcp_dp.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcs_dp.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_lmd_dp.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_pid_dp.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_rep_dp.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sbd_dp.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sed_dp.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_spd_dp.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tgd_dp.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tld_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cel_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cep_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cer_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cth_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_dfd_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ecd_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ecg_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_eem_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_mbd_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_npc_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_pct_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ssd_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_sse_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tel_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tic_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tsb_dp.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tsd_dp.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_asd_dp.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_ase_dp.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_eem_dp.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_htd_dp.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mbd_dp.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mec_dp.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mel_dp.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mem_dp.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_sed_dp.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_seg_dp.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_sel_dp.v
$DV_ROOT/design/sys/iop/spc/exu/rtl/exu_edp_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/pcx_bfg_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/pcx_mbr_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/pcx_mcl_dp.v
$DV_ROOT/design/sys/iop/ccx/rtl/pcx_rep_dp.v
$DV_ROOT/design/sys/iop/spc/pku/rtl/pku_pkd_dp.v
$DV_ROOT/design/sys/iop/spc/pmu/rtl/pmu_pdp_dp.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_adc_ctl.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_arc_ctl.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_asc_ctl.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_cic_ctl.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dac_ctl.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcc_ctl.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_lmc_ctl.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_lru8_ctl.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_pic_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_red_ctl.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sbc_ctl.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sbs_ctl.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sec_ctl.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tgc_ctl.v
$DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tlc_ctl.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_asi_ctl.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cxi_ctl.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_fls_ctl.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ras_ctl.v
$DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_trl_ctl.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_csm_ctl.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_lsi_ctl.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_msb_ctl.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_asi_ctl.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_cms_ctl.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_ftp_ctl.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_itc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_red_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_tfc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_tsm_ctl.v
$DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ibu_ibq_ctl.v
$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fac_ctl.v
$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fdc_ctl.v
$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fec_ctl.v
$DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fic_ctl.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_tmc_ctl.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_asi_ctl.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_trc_ctl.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_trs_ctl.v
$DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_tsm_ctl.v
$DV_ROOT/design/sys/iop/spc/dec/rtl/dec_ded_ctl.v
$DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_leg_ctl.v
$DV_ROOT/libs/rtl/n2_efuhdr1_ctl.v
$DV_ROOT/design/sys/iop/spc/pku/rtl/pku_swl_ctl.v
$DV_ROOT/design/sys/iop/spc/pku/rtl/pku_pck_ctl.v
$DV_ROOT/design/sys/iop/spc/exu/rtl/exu_ect_ctl.v
$DV_ROOT/design/sys/iop/spc/exu/rtl/exu_ecc_ctl.v
$DV_ROOT/design/sys/iop/spc/exu/rtl/exu_rml_ctl.v
$DV_ROOT/design/sys/iop/spc/pmu/rtl/pmu_pct_ctl.v
$DV_ROOT/design/sys/iop/ccx/rtl/ccx_arc_ctl.v
$DV_ROOT/design/sys/iop/ccx/rtl/ccx_srq_ctl.v
$DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_pqm_ctl.v
$DV_ROOT/libs/tisram/core/n2_ict_sp_1920b_cust_l/n2_ict_sp_1920b_cust/rtl/n2_ict_sp_1920b_cust.v
$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x84_cust_l/n2_com_dp_32x84_cust/rtl/n2_com_dp_32x84_cust.v
$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x72_cust_l/n2_com_dp_32x72_cust/rtl/n2_com_dp_32x72_cust.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsd.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsa.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsc.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsg.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsf.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpse.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_arb.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpa.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsb.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_mar_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpa.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsb.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsd.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpse.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsh.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsf.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_rep.v
-v $DV_ROOT/libs/cl/cl_u1/cl_u1.v
-v $DV_ROOT/libs/cl/cl_sc1/cl_sc1.v
-v $DV_ROOT/libs/cl/cl_mc1/cl_mc1.v
-v $DV_ROOT/libs/cl/cl_dp1/cl_dp1.v
-v $DV_ROOT/libs/cl/cl_rtl_ext.v
-v $DV_ROOT/libs/tisram/soc/n2_l2d_sp_512kb_cust_l/n2_l2d_sp_512kb_cust/rtl/n2_l2d_sp_512kb_cust.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsa.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsc.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsg.v
$DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_spc_cmp_cust/rtl/n2_clk_spc_cmp_cust.v
$DV_ROOT/libs/tisram/core/n2_dca_sp_9kb_cust_l/n2_dca_sp_9kb_cust/rtl/n2_dca_sp_9kb_cust.v
$DV_ROOT/libs/clk/n2_flop_bank_cust_l/n2_flop_bank_cust/rtl/n2_flop_bank_cust.v
$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x152_cust_l/n2_com_dp_32x152_cust/rtl/n2_com_dp_32x152_cust.v
$DV_ROOT/libs/n2sram/dp/n2_dva_dp_32x32_cust_l/n2_dva_dp_32x32_cust/rtl/n2_dva_dp_32x32_cust.v
$DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_64x84_cust_l/n2_com_dp_64x84_cust/rtl/n2_com_dp_64x84_cust.v
$DV_ROOT/libs/n2sram/mp/n2_irf_mp_128x72_cust_l/n2_irf_mp_128x72_cust/rtl/n2_irf_mp_128x72_cust.v
$DV_ROOT/libs/n2sram/mp/n2_frf_mp_256x78_cust_l/n2_frf_mp_256x78_cust/rtl/n2_frf_mp_256x78_cust.v
$DV_ROOT/libs/tisram/core/n2_icd_sp_16p5kb_cust_l/n2_icd_sp_16p5kb_cust/rtl/n2_icd_sp_16p5kb_cust.v
$DV_ROOT/libs/n2sram/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl/n2_tlb_tl_64x59_cust.v
$DV_ROOT/libs/n2sram/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl/n2_tlb_tl_128x59_cust.v
$DV_ROOT/libs/n2sram/cams/n2_stb_cm_64x45_cust_l/n2_stb_cm_64x45_cust/rtl/n2_stb_cm_64x45_cust.v
$DV_ROOT/libs/tisram/core/n2_dta_sp_1920b_cust_l/n2_dta_sp_1920b_cust/rtl/n2_dta_sp_1920b_cust.v