design/sys/iop/ccu/rtl/ccu_pulse_shift.v

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// OpenSPARC T2 Processor File: ccu_pulse_shift.v
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`timescale 1 ns / 1 ns

module ccu_pulse_shift (
        rst_n,
        clk,
        shift,
        pulse_in,
        pulse_out
);

input   rst_n;
input   clk;
input   [4:0] shift;
input   pulse_in;
output  pulse_out;

wire    rst_n;
wire    clk;
wire    [4:0] shift;
wire    pulse_in;
wire    pulse_out;

reg             [4:0] cnt;                      // shift counter
reg     pulse_event;            // sticky bit set hi once pulse is seen

assign  pulse_out = ((cnt[4:0] == shift[4:0]) && pulse_event)?1'b1:1'b0;

always @ (posedge clk) begin
        if (!rst_n) begin
                cnt <= 5'h00;
                pulse_event <= 1'b0;
        end     else
                if (pulse_in) begin
                        pulse_event <= 1'b1;
                        cnt <= 5'h00;
                end else begin
                        pulse_event <= pulse_event;
                        cnt <= cnt + 1'b1;
                end
end


endmodule