// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_clu_crm_psbctlfsm.v
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// ========== Copyright Header End ============================================
module dmu_clu_crm_psbctlfsm
// synopsys sync_set_reset "rst_l"
// >>>>>>>>>>>>>>>>>>>>>>>>> Parameter Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------
// --------------------------------------------------------
// --------------------------------------------------------
// --------------------------------------------------------
parameter // summit enum cur_enum
// --------------------------------------------------------
// --------------------------------------------------------
parameter PSB_PIO_WR = 4'b1100,
// >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------
// --------------------------------------------------------
// --------------------------------------------------------
// --------------------------------------------------------
// --------------------------------------------------------
// --------------------------------------------------------
output [(`FIRE_DLC_PSR_CMD_TYPE_WDTH - 1):0] cl2ps_e_cmd_type;
output [4:0] psbctlfsm_state;
// >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
// ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTERS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
// ********** Flops **********
reg [(STATE_NUM - 1):0] cur_state;
reg [(`FIRE_DLC_PSR_CMD_TYPE_WDTH - 1):0] cl2ps_e_cmd_type;
// ********** Non-Flops ******
reg [(STATE_NUM - 1):0] nxt_state;
// >>>>>>>>>>>>>>>>>>>>>>>>> 0-in Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
// 0in one_hot -var cur_state
-val (5'b1 << DMA_PSBRDCLR)
-next (5'b1 << DMA_PSBRDCLR_WAIT)
-val (5'b1 << DMA_PSBRDCLR_WAIT)
-next (5'b1 << DMA_PSBRDCLR_WAIT)
-next (5'b1 << PIO_PSBWR_WAIT)
-val (5'b1 << PIO_PSBWR_WAIT)
-next (5'b1 << PIO_PSBWR_WAIT)
// >>>>>>>>>>>>>>>>>>>>>>>>> RTL Model <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
// --------------------------------------------------------
// --------------------------------------------------------
assign psbctlfsm_idle = cur_state[IDLE];
// --------------------------------------------------------
// --------------------------------------------------------
assign psbctlfsm_state = cur_state;
// --------------------------------------------------------
// --------------------------------------------------------
always @(cur_state or start_psb_op or psb_op_typ or ps2cl_e_gnt)
nxt_state = {STATE_NUM{1'b0}};
case (1'b1) // synopsys parallel_case
///////////////////////////////////////////////////////////////////////
casez ({start_psb_op, psb_op_typ})
// 0in < case -parallel -full
3'b0_zz : nxt_state[IDLE] = 1'b1;
3'b1_10 : nxt_state[DMA_PSBRDCLR] = 1'b1;
3'b1_01 : nxt_state[PIO_PSBWR] = 1'b1;
///////////////////////////////////////////////////////////////////////
// ---------- DMA READ/CLEAR --------------------------------
cur_state[DMA_PSBRDCLR] :
nxt_state[DMA_PSBRDCLR_WAIT] = 1'b1;
// PSB READ/CLEAR WAIT State
cur_state[DMA_PSBRDCLR_WAIT] :
casez ({ps2cl_e_gnt, start_psb_op, psb_op_typ})
// 0in < case -parallel -full
4'b0_z_zz : nxt_state[DMA_PSBRDCLR_WAIT] = 1'b1;
4'b1_0_zz : nxt_state[IDLE] = 1'b1;
4'b1_1_10 : nxt_state[DMA_PSBRDCLR] = 1'b1;
4'b1_1_01 : nxt_state[PIO_PSBWR] = 1'b1;
///////////////////////////////////////////////////////////////////////
// ---------- PIO READ --------------------------------------
nxt_state[PIO_PSBWR_WAIT] = 1'b1;
cur_state[PIO_PSBWR_WAIT] :
casez ({ps2cl_e_gnt, start_psb_op, psb_op_typ})
// 0in < case -parallel -full
4'b0_z_zz : nxt_state[PIO_PSBWR_WAIT] = 1'b1;
4'b1_0_zz : nxt_state[IDLE] = 1'b1;
4'b1_1_10 : nxt_state[DMA_PSBRDCLR] = 1'b1;
4'b1_1_01 : nxt_state[PIO_PSBWR] = 1'b1;
///////////////////////////////////////////////////////////////////////
// --------------------------------------------------------
// --------------------------------------------------------
// summit state_vector cur_state enum cur_enum
// current state assignment
cur_state <= {STATE_NUM{1'b0}};
// --------------------------------------------------------
// --------------------------------------------------------
// ----- psb access status ---------------------------------
// psb access op (rd/wr) done
assign done_psb_op = (ps2cl_e_gnt & (cur_state[DMA_PSBRDCLR_WAIT] |
cur_state[PIO_PSBWR_WAIT]));
assign done_psb_rd = ps2cl_e_gnt & cur_state[DMA_PSBRDCLR_WAIT];
// ----- psb interface control -----------------------------
// psb access command type
cl2ps_e_cmd_type <= `FIRE_DLC_PSR_CMD_TYPE_WDTH'b0; // reset
else if (nxt_state[PIO_PSBWR])
cl2ps_e_cmd_type <= PSB_PIO_WR; // pio : psb wr operation
else if (nxt_state[DMA_PSBRDCLR])
cl2ps_e_cmd_type <= PSB_DMA_RDCLR; // dma : psb rd/clr operation
endmodule // dmu_clu_crm_psbctlfsm