design/sys/iop/dmu/rtl/dmu_cmu_ctx_pkseqaloc.v

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//
// OpenSPARC T2 Processor File: dmu_cmu_ctx_pkseqaloc.v
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module dmu_cmu_ctx_pkseqaloc (
                clk,
                rst_l,
        enq,
                data_in,
        deq,
                data_out,
                valid
     );

//************************************************
//                              PARAMETERS
//************************************************
   parameter WIDTH = 6;     // max width supported
   parameter DEPTH = 64;    // max depth supported

  integer        n;

//************************************************
//                              PORTS
//************************************************

  input clk;                        // The input clock
  input rst_l;                      // synopsys sync_set_reset "rst_l"

  input enq;                        // enqueue into list
  input [WIDTH - 1:0] data_in;      // data to put in

  input deq;                        // dequeue outof list
  output [WIDTH - 1:0] data_out;    // data taken out
  output valid;                     // next address Ok to allocate

//************************************************
//                              SIGNALS
//************************************************
  reg [DEPTH -1 :0] vld;                   // =1 -> address available
                                           // =0 -> address allocated already

  reg [WIDTH -1 :0] count;                 // addresses to output


//*********************************************
// list counter, updates on deq asserted
//*********************************************

always @ (posedge clk)
begin
  if (!rst_l) begin
       count <= 0;
    end
 else begin
  case (deq)
   1'b0: count <= count;
   1'b1: count <= count + 1'b1;
  endcase
 end
end

//*********************************************
// valid contents, updates when enq asserted
//*********************************************

always @ (posedge clk)
begin
  if (!rst_l) begin
         for ( n = 0; n < DEPTH ; n = n+1)
           vld[n] <= 1'b1;
  end
  else begin
     case ({enq, deq})  // synopsys full_case parallel_case
       2'b01 : vld[count]   <= 1'b0;
       2'b10 : vld[data_in] <= 1'b1;
       2'b11 : begin
                  vld[data_in] <= 1'b1;
//bug 1908
                  vld[count]   <= 1'b0;
//
           end
       default : begin
                  for ( n = 0; n < DEPTH ; n = n+1)
                         vld[n] <= vld[n];
           end
         endcase // case({enq, deq})
  end // else: !if(!rst_l)
end // always @ (posedge clk)


//************************************************
// Outputs
//************************************************

  assign data_out = count[WIDTH -1 :0];
  assign valid = vld[count];

endmodule