design/sys/iop/dmu/rtl/dmu_cru_defines.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: dmu_cru_defines.h
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* otherwise unspecified.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
*
* ========== Copyright Header End ============================================
*/
`ifdef FIRE_DLC_CRU_DEFINES
`else
`define FIRE_DLC_CRU_DEFINES

`define FIRE_DLC_CRU_INSTANCE_ID_VALUE_A 1'h0
`define FIRE_DLC_CRU_INSTANCE_ID_VALUE_B 1'h1

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_cru_csr_dmc_dbg_sel_a_reg
//-------------------------------------------------------

`define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_HW_ADDR    27'b000000011001010011000000000
`define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_A_REG_ADDR       30'b000000011001010011000000000000
`define FIRE_DLC_CRU_CSR_B_DMC_DBG_SEL_A_REG_HW_ADDR    27'b000000011101010011000000000
`define FIRE_DLC_CRU_CSR_B_DMC_DBG_SEL_A_REG_ADDR       30'b000000011101010011000000000000

`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_WIDTH        64
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_DEPTH        1
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SLC  63:0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_INT_SLC      63:0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_POSITION     0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_LOW_ADDR_WIDTH       0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_ADDR_RANGE   26:0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_READ_MASK    64'b0000000000000000000000000000000000000000000000000000001111111111
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_READ_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_WRITE_MASK   64'b0000000000000000000000000000000000000000000000000000001111111111
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_WRITE_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SET_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_CLEAR_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_TOGGLE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_RMASK        64'b0000000000000000000000000000000000000000000000000000001111111111
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_RESERVED_BIT_MASK    64'b1111111111111111111111111111111111111111111111111111110000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_POR_VALUE    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_INTERNAL_REG 1
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_ZERO_TIME_OMNI       1
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_NUM_FIELDS   3
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_FID        0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_SLC        9:6
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_WIDTH      4
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_INT_SLC    3:0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_POSITION   6
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_FMASK      64'b0000000000000000000000000000000000000000000000000000001111000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_BLOCK_SEL_POR_VALUE  4'b0000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_FID  1
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_SLC  5:3
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_WIDTH        3
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_INT_SLC      2:0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_POSITION     3
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_FMASK        64'b0000000000000000000000000000000000000000000000000000000000111000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SUB_SEL_POR_VALUE    3'b000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_FID       2
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_SLC       2:0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_WIDTH     3
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_INT_SLC   2:0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_POSITION  0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000111
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_A_REG_SIGNAL_SEL_POR_VALUE 3'b000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_cru_csr_dmc_dbg_sel_b_reg
//-------------------------------------------------------

`define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_HW_ADDR    27'b000000011001010011000000001
`define FIRE_DLC_CRU_CSR_A_DMC_DBG_SEL_B_REG_ADDR       30'b000000011001010011000000001000
`define FIRE_DLC_CRU_CSR_B_DMC_DBG_SEL_B_REG_HW_ADDR    27'b000000011101010011000000001
`define FIRE_DLC_CRU_CSR_B_DMC_DBG_SEL_B_REG_ADDR       30'b000000011101010011000000001000

`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_WIDTH        64
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_DEPTH        1
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SLC  63:0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_INT_SLC      63:0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_POSITION     0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_LOW_ADDR_WIDTH       0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_ADDR_RANGE   26:0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_READ_MASK    64'b0000000000000000000000000000000000000000000000000000001111111111
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_READ_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_WRITE_MASK   64'b0000000000000000000000000000000000000000000000000000001111111111
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_WRITE_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SET_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_CLEAR_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_TOGGLE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_RMASK        64'b0000000000000000000000000000000000000000000000000000001111111111
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_RESERVED_BIT_MASK    64'b1111111111111111111111111111111111111111111111111111110000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_POR_VALUE    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_INTERNAL_REG 1
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_ZERO_TIME_OMNI       1
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_NUM_FIELDS   3
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_FID        0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_SLC        9:6
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_WIDTH      4
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_INT_SLC    3:0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_POSITION   6
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_FMASK      64'b0000000000000000000000000000000000000000000000000000001111000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_POR_VALUE  4'b0000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_FID  1
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_SLC  5:3
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_WIDTH        3
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_INT_SLC      2:0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_POSITION     3
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_FMASK        64'b0000000000000000000000000000000000000000000000000000000000111000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_HW_LD_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_POR_VALUE    3'b000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_FID       2
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_SLC       2:0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_WIDTH     3
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_INT_SLC   2:0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_POSITION  0
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_FMASK     64'b0000000000000000000000000000000000000000000000000000000000000111
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_POR_VALUE 3'b000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_cru_csr_dmc_pcie_cfg
//-------------------------------------------------------

`define FIRE_DLC_CRU_CSR_A_DMC_PCIE_CFG_HW_ADDR 27'b000000011001010011000100000
`define FIRE_DLC_CRU_CSR_A_DMC_PCIE_CFG_ADDR    30'b000000011001010011000100000000
`define FIRE_DLC_CRU_CSR_B_DMC_PCIE_CFG_HW_ADDR 27'b000000011101010011000100000
`define FIRE_DLC_CRU_CSR_B_DMC_PCIE_CFG_ADDR    30'b000000011101010011000100000000

`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_WIDTH     64
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_DEPTH     1
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_SLC       63:0
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_INT_SLC   63:0
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_POSITION  0
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_LOW_ADDR_WIDTH    0
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_ADDR_RANGE        26:0
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_READ_MASK 64'b0000000000000000000000000000000011111111000000001111111111111111
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_READ_ONLY_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_WRITE_MASK        64'b0000000000000000000000000000000011111111000000001111111111111111
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_WRITE_ONLY_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_SET_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_CLEAR_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_TOGGLE_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_RMASK     64'b0000000000000000000000000000000011111111000000001111111111111111
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111100000000111111110000000000000000
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_INTERNAL_REG      1
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_ZERO_TIME_OMNI    1
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_NUM_FIELDS        2
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_FID       0
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_SLC       31:24
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_WIDTH     8
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_INT_SLC   7:0
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_POSITION  24
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_FMASK     64'b0000000000000000000000000000000011111111000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_BUS_NUM_POR_VALUE 8'b00000000
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_FID        1
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_SLC        15:0
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_WIDTH      16
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_INT_SLC    15:0
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_POSITION   0
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_FMASK      64'b0000000000000000000000000000000000000000000000001111111111111111
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_CRU_CSR_DMC_PCIE_CFG_REQ_ID_POR_VALUE  16'b0000000000000000


`endif