// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_ilu_cib_csr_ilu_diagnos_entry.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
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// GNU General Public License for more details.
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// ========== Copyright Header End ============================================
module dmu_ilu_cib_csr_ilu_diagnos_entry
// synopsys translate_off
ilu_diagnos_csrbus_read_data,
ilu_diagnos_edi_trig_hw_clr,
ilu_diagnos_ehi_trig_hw_clr
//====================================================================
//====================================================================
// synopsys translate_off
input omni_ld; // Omni load
// vlint flag_input_port_not_connected off
input [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_WIDTH - 1:0] omni_data;
// vlint flag_input_port_not_connected on
input clk; // Clock signal
input rst_l; // Reset signal
input por_l; // Reset signal
// vlint flag_input_port_not_connected off
input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_input_port_not_connected on
output [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_WIDTH-1:0] ilu_diagnos_csrbus_read_data;
input ilu_diagnos_edi_trig_hw_clr; // Hardware clear signal for
// ilu_diagnos_edi_trig. When set
// ilu_diagnos will be set to zero.
input ilu_diagnos_ehi_trig_hw_clr; // Hardware clear signal for
// ilu_diagnos_ehi_trig. When set
// ilu_diagnos will be set to zero.
//====================================================================
//====================================================================
// synopsys translate_off
wire omni_ld; // Omni load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_WIDTH - 1:0] omni_data;
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire clk; // Clock signal
wire rst_l; // Reset signal
wire por_l; // Reset signal
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire [`FIRE_DLC_ILU_CIB_CSR_ILU_DIAGNOS_WIDTH-1:0] ilu_diagnos_csrbus_read_data;
wire ilu_diagnos_edi_trig_hw_clr; // Hardware clear signal for
// ilu_diagnos_edi_trig. When set ilu_diagnos
wire ilu_diagnos_ehi_trig_hw_clr; // Hardware clear signal for
// ilu_diagnos_ehi_trig. When set ilu_diagnos
//====================================================================
//====================================================================
wire [0:0] reset_enpll1 = 1'h1;
wire [0:0] reset_enpll0 = 1'h1;
wire [0:0] reset_entx7 = 1'h1;
wire [0:0] reset_entx6 = 1'h1;
wire [0:0] reset_entx5 = 1'h1;
wire [0:0] reset_entx4 = 1'h1;
wire [0:0] reset_entx3 = 1'h1;
wire [0:0] reset_entx2 = 1'h1;
wire [0:0] reset_entx1 = 1'h1;
wire [0:0] reset_entx0 = 1'h1;
wire [0:0] reset_enrx7 = 1'h1;
wire [0:0] reset_enrx6 = 1'h1;
wire [0:0] reset_enrx5 = 1'h1;
wire [0:0] reset_enrx4 = 1'h1;
wire [0:0] reset_enrx3 = 1'h1;
wire [0:0] reset_enrx2 = 1'h1;
wire [0:0] reset_enrx1 = 1'h1;
wire [0:0] reset_enrx0 = 1'h1;
wire [3:0] reset_edi_par = 4'h0;
wire [3:0] reset_ehi_par = 4'h0;
wire [0:0] reset_edi_trig = 1'h0;
wire [0:0] reset_ehi_trig = 1'h0;
wire [1:0] reset_rate_scale = 2'h0;
//----- Active high reset wires
wire rst_l_active_high = ~rst_l;
wire por_l_active_high = ~por_l;
//====================================================
// Instantiation of flops
//====================================================
assign ilu_diagnos_csrbus_read_data[0] = 1'b0; // bit 0
assign ilu_diagnos_csrbus_read_data[1] = 1'b0; // bit 1
// synopsys translate_off
.omni_data (omni_data[2]),
.rst (por_l_active_high),
.rst_val (reset_rate_scale[0]),
.csr_data (csrbus_wr_data[2]),
.q (ilu_diagnos_csrbus_read_data[2])
// synopsys translate_off
.omni_data (omni_data[3]),
.rst (por_l_active_high),
.rst_val (reset_rate_scale[1]),
.csr_data (csrbus_wr_data[3]),
.q (ilu_diagnos_csrbus_read_data[3])
// synopsys translate_off
.omni_data (omni_data[4]),
.rst (rst_l_active_high),
.rst_val (reset_ehi_trig[0]),
.csr_data (csrbus_wr_data[4]),
.hw_ld (ilu_diagnos_ehi_trig_hw_clr),
.q (ilu_diagnos_csrbus_read_data[4])
// synopsys translate_off
.omni_data (omni_data[5]),
.rst (rst_l_active_high),
.rst_val (reset_edi_trig[0]),
.csr_data (csrbus_wr_data[5]),
.hw_ld (ilu_diagnos_edi_trig_hw_clr),
.q (ilu_diagnos_csrbus_read_data[5])
assign ilu_diagnos_csrbus_read_data[6] = 1'b0; // bit 6
assign ilu_diagnos_csrbus_read_data[7] = 1'b0; // bit 7
// synopsys translate_off
.omni_data (omni_data[8]),
.rst (rst_l_active_high),
.rst_val (reset_ehi_par[0]),
.csr_data (csrbus_wr_data[8]),
.q (ilu_diagnos_csrbus_read_data[8])
// synopsys translate_off
.omni_data (omni_data[9]),
.rst (rst_l_active_high),
.rst_val (reset_ehi_par[1]),
.csr_data (csrbus_wr_data[9]),
.q (ilu_diagnos_csrbus_read_data[9])
// synopsys translate_off
.omni_data (omni_data[10]),
.rst (rst_l_active_high),
.rst_val (reset_ehi_par[2]),
.csr_data (csrbus_wr_data[10]),
.q (ilu_diagnos_csrbus_read_data[10])
// synopsys translate_off
.omni_data (omni_data[11]),
.rst (rst_l_active_high),
.rst_val (reset_ehi_par[3]),
.csr_data (csrbus_wr_data[11]),
.q (ilu_diagnos_csrbus_read_data[11])
// synopsys translate_off
.omni_data (omni_data[12]),
.rst (rst_l_active_high),
.rst_val (reset_edi_par[0]),
.csr_data (csrbus_wr_data[12]),
.q (ilu_diagnos_csrbus_read_data[12])
// synopsys translate_off
.omni_data (omni_data[13]),
.rst (rst_l_active_high),
.rst_val (reset_edi_par[1]),
.csr_data (csrbus_wr_data[13]),
.q (ilu_diagnos_csrbus_read_data[13])
// synopsys translate_off
.omni_data (omni_data[14]),
.rst (rst_l_active_high),
.rst_val (reset_edi_par[2]),
.csr_data (csrbus_wr_data[14]),
.q (ilu_diagnos_csrbus_read_data[14])
// synopsys translate_off
.omni_data (omni_data[15]),
.rst (rst_l_active_high),
.rst_val (reset_edi_par[3]),
.csr_data (csrbus_wr_data[15]),
.q (ilu_diagnos_csrbus_read_data[15])
// synopsys translate_off
.omni_data (omni_data[16]),
.rst (rst_l_active_high),
.rst_val (reset_enrx0[0]),
.csr_data (csrbus_wr_data[16]),
.q (ilu_diagnos_csrbus_read_data[16])
// synopsys translate_off
.omni_data (omni_data[17]),
.rst (rst_l_active_high),
.rst_val (reset_enrx1[0]),
.csr_data (csrbus_wr_data[17]),
.q (ilu_diagnos_csrbus_read_data[17])
// synopsys translate_off
.omni_data (omni_data[18]),
.rst (rst_l_active_high),
.rst_val (reset_enrx2[0]),
.csr_data (csrbus_wr_data[18]),
.q (ilu_diagnos_csrbus_read_data[18])
// synopsys translate_off
.omni_data (omni_data[19]),
.rst (rst_l_active_high),
.rst_val (reset_enrx3[0]),
.csr_data (csrbus_wr_data[19]),
.q (ilu_diagnos_csrbus_read_data[19])
// synopsys translate_off
.omni_data (omni_data[20]),
.rst (rst_l_active_high),
.rst_val (reset_enrx4[0]),
.csr_data (csrbus_wr_data[20]),
.q (ilu_diagnos_csrbus_read_data[20])
// synopsys translate_off
.omni_data (omni_data[21]),
.rst (rst_l_active_high),
.rst_val (reset_enrx5[0]),
.csr_data (csrbus_wr_data[21]),
.q (ilu_diagnos_csrbus_read_data[21])
// synopsys translate_off
.omni_data (omni_data[22]),
.rst (rst_l_active_high),
.rst_val (reset_enrx6[0]),
.csr_data (csrbus_wr_data[22]),
.q (ilu_diagnos_csrbus_read_data[22])
// synopsys translate_off
.omni_data (omni_data[23]),
.rst (rst_l_active_high),
.rst_val (reset_enrx7[0]),
.csr_data (csrbus_wr_data[23]),
.q (ilu_diagnos_csrbus_read_data[23])
// synopsys translate_off
.omni_data (omni_data[24]),
.rst (rst_l_active_high),
.rst_val (reset_entx0[0]),
.csr_data (csrbus_wr_data[24]),
.q (ilu_diagnos_csrbus_read_data[24])
// synopsys translate_off
.omni_data (omni_data[25]),
.rst (rst_l_active_high),
.rst_val (reset_entx1[0]),
.csr_data (csrbus_wr_data[25]),
.q (ilu_diagnos_csrbus_read_data[25])
// synopsys translate_off
.omni_data (omni_data[26]),
.rst (rst_l_active_high),
.rst_val (reset_entx2[0]),
.csr_data (csrbus_wr_data[26]),
.q (ilu_diagnos_csrbus_read_data[26])
// synopsys translate_off
.omni_data (omni_data[27]),
.rst (rst_l_active_high),
.rst_val (reset_entx3[0]),
.csr_data (csrbus_wr_data[27]),
.q (ilu_diagnos_csrbus_read_data[27])
// synopsys translate_off
.omni_data (omni_data[28]),
.rst (rst_l_active_high),
.rst_val (reset_entx4[0]),
.csr_data (csrbus_wr_data[28]),
.q (ilu_diagnos_csrbus_read_data[28])
// synopsys translate_off
.omni_data (omni_data[29]),
.rst (rst_l_active_high),
.rst_val (reset_entx5[0]),
.csr_data (csrbus_wr_data[29]),
.q (ilu_diagnos_csrbus_read_data[29])
// synopsys translate_off
.omni_data (omni_data[30]),
.rst (rst_l_active_high),
.rst_val (reset_entx6[0]),
.csr_data (csrbus_wr_data[30]),
.q (ilu_diagnos_csrbus_read_data[30])
// synopsys translate_off
.omni_data (omni_data[31]),
.rst (rst_l_active_high),
.rst_val (reset_entx7[0]),
.csr_data (csrbus_wr_data[31]),
.q (ilu_diagnos_csrbus_read_data[31])
// synopsys translate_off
.omni_data (omni_data[32]),
.rst (rst_l_active_high),
.rst_val (reset_enpll0[0]),
.csr_data (csrbus_wr_data[32]),
.q (ilu_diagnos_csrbus_read_data[32])
// synopsys translate_off
.omni_data (omni_data[33]),
.rst (rst_l_active_high),
.rst_val (reset_enpll1[0]),
.csr_data (csrbus_wr_data[33]),
.q (ilu_diagnos_csrbus_read_data[33])
assign ilu_diagnos_csrbus_read_data[34] = 1'b0; // bit 34
assign ilu_diagnos_csrbus_read_data[35] = 1'b0; // bit 35
assign ilu_diagnos_csrbus_read_data[36] = 1'b0; // bit 36
assign ilu_diagnos_csrbus_read_data[37] = 1'b0; // bit 37
assign ilu_diagnos_csrbus_read_data[38] = 1'b0; // bit 38
assign ilu_diagnos_csrbus_read_data[39] = 1'b0; // bit 39
assign ilu_diagnos_csrbus_read_data[40] = 1'b0; // bit 40
assign ilu_diagnos_csrbus_read_data[41] = 1'b0; // bit 41
assign ilu_diagnos_csrbus_read_data[42] = 1'b0; // bit 42
assign ilu_diagnos_csrbus_read_data[43] = 1'b0; // bit 43
assign ilu_diagnos_csrbus_read_data[44] = 1'b0; // bit 44
assign ilu_diagnos_csrbus_read_data[45] = 1'b0; // bit 45
assign ilu_diagnos_csrbus_read_data[46] = 1'b0; // bit 46
assign ilu_diagnos_csrbus_read_data[47] = 1'b0; // bit 47
assign ilu_diagnos_csrbus_read_data[48] = 1'b0; // bit 48
assign ilu_diagnos_csrbus_read_data[49] = 1'b0; // bit 49
assign ilu_diagnos_csrbus_read_data[50] = 1'b0; // bit 50
assign ilu_diagnos_csrbus_read_data[51] = 1'b0; // bit 51
assign ilu_diagnos_csrbus_read_data[52] = 1'b0; // bit 52
assign ilu_diagnos_csrbus_read_data[53] = 1'b0; // bit 53
assign ilu_diagnos_csrbus_read_data[54] = 1'b0; // bit 54
assign ilu_diagnos_csrbus_read_data[55] = 1'b0; // bit 55
assign ilu_diagnos_csrbus_read_data[56] = 1'b0; // bit 56
assign ilu_diagnos_csrbus_read_data[57] = 1'b0; // bit 57
assign ilu_diagnos_csrbus_read_data[58] = 1'b0; // bit 58
assign ilu_diagnos_csrbus_read_data[59] = 1'b0; // bit 59
assign ilu_diagnos_csrbus_read_data[60] = 1'b0; // bit 60
assign ilu_diagnos_csrbus_read_data[61] = 1'b0; // bit 61
assign ilu_diagnos_csrbus_read_data[62] = 1'b0; // bit 62
assign ilu_diagnos_csrbus_read_data[63] = 1'b0; // bit 63
endmodule // dmu_ilu_cib_csr_ilu_diagnos_entry