// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_imu_ics_csr_mem_64_pcie_offset_reg_entry.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
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// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
module dmu_imu_ics_csr_mem_64_pcie_offset_reg_entry
// synopsys translate_off
mem_64_pcie_offset_reg_csrbus_read_data,
mem_64_pcie_offset_reg_spare_control_load_7_hw_ld,
mem_64_pcie_offset_reg_spare_control_load_7_hw_write,
mem_64_pcie_offset_reg_spare_control_load_6_hw_ld,
mem_64_pcie_offset_reg_spare_control_load_6_hw_write,
mem_64_pcie_offset_reg_spare_control_load_5_hw_ld,
mem_64_pcie_offset_reg_spare_control_load_5_hw_write,
mem_64_pcie_offset_reg_spare_control_load_4_hw_ld,
mem_64_pcie_offset_reg_spare_control_load_4_hw_write,
mem_64_pcie_offset_reg_spare_control_load_3_hw_ld,
mem_64_pcie_offset_reg_spare_control_load_3_hw_write,
mem_64_pcie_offset_reg_spare_control_load_2_hw_ld,
mem_64_pcie_offset_reg_spare_control_load_2_hw_write,
mem_64_pcie_offset_reg_spare_control_load_1_hw_ld,
mem_64_pcie_offset_reg_spare_control_load_1_hw_write,
mem_64_pcie_offset_reg_spare_control_load_0_hw_ld,
mem_64_pcie_offset_reg_spare_control_load_0_hw_write,
mem_64_pcie_offset_reg_spare_control_hw_write
//====================================================================
//====================================================================
// synopsys translate_off
input omni_ld; // Omni load
// vlint flag_input_port_not_connected off
input [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_WIDTH - 1:0] omni_data;
// vlint flag_input_port_not_connected on
input clk; // Clock signal
input rst_l; // Reset signal
// vlint flag_input_port_not_connected off
input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_input_port_not_connected on
output [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_WIDTH-1:0] mem_64_pcie_offset_reg_csrbus_read_data;
input mem_64_pcie_offset_reg_spare_control_load_7_hw_ld; // Hardware load
// mem_64_pcie_offset_reg_spare_control_load_7.
// mem_64_pcie_offset_reg.
input mem_64_pcie_offset_reg_spare_control_load_7_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_7.
input mem_64_pcie_offset_reg_spare_control_load_6_hw_ld; // Hardware load
// mem_64_pcie_offset_reg_spare_control_load_6.
// mem_64_pcie_offset_reg.
input mem_64_pcie_offset_reg_spare_control_load_6_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_6.
input mem_64_pcie_offset_reg_spare_control_load_5_hw_ld; // Hardware load
// mem_64_pcie_offset_reg_spare_control_load_5.
// mem_64_pcie_offset_reg.
input mem_64_pcie_offset_reg_spare_control_load_5_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_5.
input mem_64_pcie_offset_reg_spare_control_load_4_hw_ld; // Hardware load
// mem_64_pcie_offset_reg_spare_control_load_4.
// mem_64_pcie_offset_reg.
input mem_64_pcie_offset_reg_spare_control_load_4_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_4.
input mem_64_pcie_offset_reg_spare_control_load_3_hw_ld; // Hardware load
// mem_64_pcie_offset_reg_spare_control_load_3.
// mem_64_pcie_offset_reg.
input mem_64_pcie_offset_reg_spare_control_load_3_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_3.
input mem_64_pcie_offset_reg_spare_control_load_2_hw_ld; // Hardware load
// mem_64_pcie_offset_reg_spare_control_load_2.
// mem_64_pcie_offset_reg.
input mem_64_pcie_offset_reg_spare_control_load_2_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_2.
input mem_64_pcie_offset_reg_spare_control_load_1_hw_ld; // Hardware load
// mem_64_pcie_offset_reg_spare_control_load_1.
// mem_64_pcie_offset_reg.
input mem_64_pcie_offset_reg_spare_control_load_1_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_1.
input mem_64_pcie_offset_reg_spare_control_load_0_hw_ld; // Hardware load
// mem_64_pcie_offset_reg_spare_control_load_0.
// mem_64_pcie_offset_reg.
input mem_64_pcie_offset_reg_spare_control_load_0_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_0.
input [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC]
mem_64_pcie_offset_reg_spare_control_hw_write; // data bus for hw loading of
// mem_64_pcie_offset_reg_spare_control.
//====================================================================
//====================================================================
// synopsys translate_off
wire omni_ld; // Omni load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_WIDTH - 1:0] omni_data;
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire clk; // Clock signal
wire rst_l; // Reset signal
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_WIDTH-1:0] mem_64_pcie_offset_reg_csrbus_read_data;
wire mem_64_pcie_offset_reg_spare_control_load_7_hw_ld; // Hardware load enable
// mem_64_pcie_offset_reg_spare_control_load_7.
// mem_64_pcie_offset_reg.
wire mem_64_pcie_offset_reg_spare_control_load_7_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_7.
wire mem_64_pcie_offset_reg_spare_control_load_6_hw_ld; // Hardware load enable
// mem_64_pcie_offset_reg_spare_control_load_6.
// mem_64_pcie_offset_reg.
wire mem_64_pcie_offset_reg_spare_control_load_6_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_6.
wire mem_64_pcie_offset_reg_spare_control_load_5_hw_ld; // Hardware load enable
// mem_64_pcie_offset_reg_spare_control_load_5.
// mem_64_pcie_offset_reg.
wire mem_64_pcie_offset_reg_spare_control_load_5_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_5.
wire mem_64_pcie_offset_reg_spare_control_load_4_hw_ld; // Hardware load enable
// mem_64_pcie_offset_reg_spare_control_load_4.
// mem_64_pcie_offset_reg.
wire mem_64_pcie_offset_reg_spare_control_load_4_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_4.
wire mem_64_pcie_offset_reg_spare_control_load_3_hw_ld; // Hardware load enable
// mem_64_pcie_offset_reg_spare_control_load_3.
// mem_64_pcie_offset_reg.
wire mem_64_pcie_offset_reg_spare_control_load_3_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_3.
wire mem_64_pcie_offset_reg_spare_control_load_2_hw_ld; // Hardware load enable
// mem_64_pcie_offset_reg_spare_control_load_2.
// mem_64_pcie_offset_reg.
wire mem_64_pcie_offset_reg_spare_control_load_2_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_2.
wire mem_64_pcie_offset_reg_spare_control_load_1_hw_ld; // Hardware load enable
// mem_64_pcie_offset_reg_spare_control_load_1.
// mem_64_pcie_offset_reg.
wire mem_64_pcie_offset_reg_spare_control_load_1_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_1.
wire mem_64_pcie_offset_reg_spare_control_load_0_hw_ld; // Hardware load enable
// mem_64_pcie_offset_reg_spare_control_load_0.
// mem_64_pcie_offset_reg.
wire mem_64_pcie_offset_reg_spare_control_load_0_hw_write; // data bus for hw
// mem_64_pcie_offset_reg_spare_control_load_0.
wire [`FIRE_DLC_IMU_ICS_CSR_MEM_64_PCIE_OFFSET_REG_SPARE_CONTROL_INT_SLC] mem_64_pcie_offset_reg_spare_control_hw_write;
// data bus for hw loading of mem_64_pcie_offset_reg_spare_control.
//====================================================================
//====================================================================
wire [39:0] reset_addr = 40'h0;
wire [0:0] reset_spare_control_load_7 = 1'h0;
wire [0:0] reset_spare_control_load_6 = 1'h0;
wire [0:0] reset_spare_control_load_5 = 1'h0;
wire [0:0] reset_spare_control_load_4 = 1'h0;
wire [0:0] reset_spare_control_load_3 = 1'h0;
wire [0:0] reset_spare_control_load_2 = 1'h0;
wire [0:0] reset_spare_control_load_1 = 1'h0;
wire [0:0] reset_spare_control_load_0 = 1'h0;
wire [7:0] reset_spare_control = 8'h0;
wire [7:0] reset_spare_status = 8'h0;
//----- Active high reset wires
wire rst_l_active_high = ~rst_l;
//====================================================
// Instantiation of flops
//====================================================
// synopsys translate_off
.omni_data (omni_data[0]),
.rst (rst_l_active_high),
.rst_val (reset_spare_status[0]),
.csr_data (csrbus_wr_data[0]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[0])
// synopsys translate_off
.omni_data (omni_data[1]),
.rst (rst_l_active_high),
.rst_val (reset_spare_status[1]),
.csr_data (csrbus_wr_data[1]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[1])
// synopsys translate_off
.omni_data (omni_data[2]),
.rst (rst_l_active_high),
.rst_val (reset_spare_status[2]),
.csr_data (csrbus_wr_data[2]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[2])
// synopsys translate_off
.omni_data (omni_data[3]),
.rst (rst_l_active_high),
.rst_val (reset_spare_status[3]),
.csr_data (csrbus_wr_data[3]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[3])
// synopsys translate_off
.omni_data (omni_data[4]),
.rst (rst_l_active_high),
.rst_val (reset_spare_status[4]),
.csr_data (csrbus_wr_data[4]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[4])
// synopsys translate_off
.omni_data (omni_data[5]),
.rst (rst_l_active_high),
.rst_val (reset_spare_status[5]),
.csr_data (csrbus_wr_data[5]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[5])
// synopsys translate_off
.omni_data (omni_data[6]),
.rst (rst_l_active_high),
.rst_val (reset_spare_status[6]),
.csr_data (csrbus_wr_data[6]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[6])
// synopsys translate_off
.omni_data (omni_data[7]),
.rst (rst_l_active_high),
.rst_val (reset_spare_status[7]),
.csr_data (csrbus_wr_data[7]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[7])
// synopsys translate_off
.omni_data (omni_data[8]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control[0]),
.csr_data (csrbus_wr_data[8]),
.hw_data (mem_64_pcie_offset_reg_spare_control_hw_write[0]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[8])
// synopsys translate_off
.omni_data (omni_data[9]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control[1]),
.csr_data (csrbus_wr_data[9]),
.hw_data (mem_64_pcie_offset_reg_spare_control_hw_write[1]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[9])
// synopsys translate_off
.omni_data (omni_data[10]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control[2]),
.csr_data (csrbus_wr_data[10]),
.hw_data (mem_64_pcie_offset_reg_spare_control_hw_write[2]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[10])
// synopsys translate_off
.omni_data (omni_data[11]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control[3]),
.csr_data (csrbus_wr_data[11]),
.hw_data (mem_64_pcie_offset_reg_spare_control_hw_write[3]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[11])
// synopsys translate_off
.omni_data (omni_data[12]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control[4]),
.csr_data (csrbus_wr_data[12]),
.hw_data (mem_64_pcie_offset_reg_spare_control_hw_write[4]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[12])
// synopsys translate_off
.omni_data (omni_data[13]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control[5]),
.csr_data (csrbus_wr_data[13]),
.hw_data (mem_64_pcie_offset_reg_spare_control_hw_write[5]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[13])
// synopsys translate_off
.omni_data (omni_data[14]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control[6]),
.csr_data (csrbus_wr_data[14]),
.hw_data (mem_64_pcie_offset_reg_spare_control_hw_write[6]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[14])
// synopsys translate_off
.omni_data (omni_data[15]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control[7]),
.csr_data (csrbus_wr_data[15]),
.hw_data (mem_64_pcie_offset_reg_spare_control_hw_write[7]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[15])
// synopsys translate_off
.omni_data (omni_data[16]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control_load_0[0]),
.csr_data (csrbus_wr_data[16]),
.hw_ld (mem_64_pcie_offset_reg_spare_control_load_0_hw_ld),
.hw_data (mem_64_pcie_offset_reg_spare_control_load_0_hw_write),
.q (mem_64_pcie_offset_reg_csrbus_read_data[16])
// synopsys translate_off
.omni_data (omni_data[17]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control_load_1[0]),
.csr_data (csrbus_wr_data[17]),
.hw_ld (mem_64_pcie_offset_reg_spare_control_load_1_hw_ld),
.hw_data (mem_64_pcie_offset_reg_spare_control_load_1_hw_write),
.q (mem_64_pcie_offset_reg_csrbus_read_data[17])
// synopsys translate_off
.omni_data (omni_data[18]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control_load_2[0]),
.csr_data (csrbus_wr_data[18]),
.hw_ld (mem_64_pcie_offset_reg_spare_control_load_2_hw_ld),
.hw_data (mem_64_pcie_offset_reg_spare_control_load_2_hw_write),
.q (mem_64_pcie_offset_reg_csrbus_read_data[18])
// synopsys translate_off
.omni_data (omni_data[19]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control_load_3[0]),
.csr_data (csrbus_wr_data[19]),
.hw_ld (mem_64_pcie_offset_reg_spare_control_load_3_hw_ld),
.hw_data (mem_64_pcie_offset_reg_spare_control_load_3_hw_write),
.q (mem_64_pcie_offset_reg_csrbus_read_data[19])
// synopsys translate_off
.omni_data (omni_data[20]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control_load_4[0]),
.csr_data (csrbus_wr_data[20]),
.hw_ld (mem_64_pcie_offset_reg_spare_control_load_4_hw_ld),
.hw_data (mem_64_pcie_offset_reg_spare_control_load_4_hw_write),
.q (mem_64_pcie_offset_reg_csrbus_read_data[20])
// synopsys translate_off
.omni_data (omni_data[21]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control_load_5[0]),
.csr_data (csrbus_wr_data[21]),
.hw_ld (mem_64_pcie_offset_reg_spare_control_load_5_hw_ld),
.hw_data (mem_64_pcie_offset_reg_spare_control_load_5_hw_write),
.q (mem_64_pcie_offset_reg_csrbus_read_data[21])
// synopsys translate_off
.omni_data (omni_data[22]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control_load_6[0]),
.csr_data (csrbus_wr_data[22]),
.hw_ld (mem_64_pcie_offset_reg_spare_control_load_6_hw_ld),
.hw_data (mem_64_pcie_offset_reg_spare_control_load_6_hw_write),
.q (mem_64_pcie_offset_reg_csrbus_read_data[22])
// synopsys translate_off
.omni_data (omni_data[23]),
.rst (rst_l_active_high),
.rst_val (reset_spare_control_load_7[0]),
.csr_data (csrbus_wr_data[23]),
.hw_ld (mem_64_pcie_offset_reg_spare_control_load_7_hw_ld),
.hw_data (mem_64_pcie_offset_reg_spare_control_load_7_hw_write),
.q (mem_64_pcie_offset_reg_csrbus_read_data[23])
// synopsys translate_off
.omni_data (omni_data[24]),
.rst (rst_l_active_high),
.rst_val (reset_addr[0]),
.csr_data (csrbus_wr_data[24]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[24])
// synopsys translate_off
.omni_data (omni_data[25]),
.rst (rst_l_active_high),
.rst_val (reset_addr[1]),
.csr_data (csrbus_wr_data[25]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[25])
// synopsys translate_off
.omni_data (omni_data[26]),
.rst (rst_l_active_high),
.rst_val (reset_addr[2]),
.csr_data (csrbus_wr_data[26]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[26])
// synopsys translate_off
.omni_data (omni_data[27]),
.rst (rst_l_active_high),
.rst_val (reset_addr[3]),
.csr_data (csrbus_wr_data[27]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[27])
// synopsys translate_off
.omni_data (omni_data[28]),
.rst (rst_l_active_high),
.rst_val (reset_addr[4]),
.csr_data (csrbus_wr_data[28]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[28])
// synopsys translate_off
.omni_data (omni_data[29]),
.rst (rst_l_active_high),
.rst_val (reset_addr[5]),
.csr_data (csrbus_wr_data[29]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[29])
// synopsys translate_off
.omni_data (omni_data[30]),
.rst (rst_l_active_high),
.rst_val (reset_addr[6]),
.csr_data (csrbus_wr_data[30]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[30])
// synopsys translate_off
.omni_data (omni_data[31]),
.rst (rst_l_active_high),
.rst_val (reset_addr[7]),
.csr_data (csrbus_wr_data[31]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[31])
// synopsys translate_off
.omni_data (omni_data[32]),
.rst (rst_l_active_high),
.rst_val (reset_addr[8]),
.csr_data (csrbus_wr_data[32]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[32])
// synopsys translate_off
.omni_data (omni_data[33]),
.rst (rst_l_active_high),
.rst_val (reset_addr[9]),
.csr_data (csrbus_wr_data[33]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[33])
// synopsys translate_off
.omni_data (omni_data[34]),
.rst (rst_l_active_high),
.rst_val (reset_addr[10]),
.csr_data (csrbus_wr_data[34]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[34])
// synopsys translate_off
.omni_data (omni_data[35]),
.rst (rst_l_active_high),
.rst_val (reset_addr[11]),
.csr_data (csrbus_wr_data[35]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[35])
// synopsys translate_off
.omni_data (omni_data[36]),
.rst (rst_l_active_high),
.rst_val (reset_addr[12]),
.csr_data (csrbus_wr_data[36]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[36])
// synopsys translate_off
.omni_data (omni_data[37]),
.rst (rst_l_active_high),
.rst_val (reset_addr[13]),
.csr_data (csrbus_wr_data[37]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[37])
// synopsys translate_off
.omni_data (omni_data[38]),
.rst (rst_l_active_high),
.rst_val (reset_addr[14]),
.csr_data (csrbus_wr_data[38]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[38])
// synopsys translate_off
.omni_data (omni_data[39]),
.rst (rst_l_active_high),
.rst_val (reset_addr[15]),
.csr_data (csrbus_wr_data[39]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[39])
// synopsys translate_off
.omni_data (omni_data[40]),
.rst (rst_l_active_high),
.rst_val (reset_addr[16]),
.csr_data (csrbus_wr_data[40]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[40])
// synopsys translate_off
.omni_data (omni_data[41]),
.rst (rst_l_active_high),
.rst_val (reset_addr[17]),
.csr_data (csrbus_wr_data[41]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[41])
// synopsys translate_off
.omni_data (omni_data[42]),
.rst (rst_l_active_high),
.rst_val (reset_addr[18]),
.csr_data (csrbus_wr_data[42]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[42])
// synopsys translate_off
.omni_data (omni_data[43]),
.rst (rst_l_active_high),
.rst_val (reset_addr[19]),
.csr_data (csrbus_wr_data[43]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[43])
// synopsys translate_off
.omni_data (omni_data[44]),
.rst (rst_l_active_high),
.rst_val (reset_addr[20]),
.csr_data (csrbus_wr_data[44]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[44])
// synopsys translate_off
.omni_data (omni_data[45]),
.rst (rst_l_active_high),
.rst_val (reset_addr[21]),
.csr_data (csrbus_wr_data[45]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[45])
// synopsys translate_off
.omni_data (omni_data[46]),
.rst (rst_l_active_high),
.rst_val (reset_addr[22]),
.csr_data (csrbus_wr_data[46]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[46])
// synopsys translate_off
.omni_data (omni_data[47]),
.rst (rst_l_active_high),
.rst_val (reset_addr[23]),
.csr_data (csrbus_wr_data[47]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[47])
// synopsys translate_off
.omni_data (omni_data[48]),
.rst (rst_l_active_high),
.rst_val (reset_addr[24]),
.csr_data (csrbus_wr_data[48]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[48])
// synopsys translate_off
.omni_data (omni_data[49]),
.rst (rst_l_active_high),
.rst_val (reset_addr[25]),
.csr_data (csrbus_wr_data[49]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[49])
// synopsys translate_off
.omni_data (omni_data[50]),
.rst (rst_l_active_high),
.rst_val (reset_addr[26]),
.csr_data (csrbus_wr_data[50]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[50])
// synopsys translate_off
.omni_data (omni_data[51]),
.rst (rst_l_active_high),
.rst_val (reset_addr[27]),
.csr_data (csrbus_wr_data[51]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[51])
// synopsys translate_off
.omni_data (omni_data[52]),
.rst (rst_l_active_high),
.rst_val (reset_addr[28]),
.csr_data (csrbus_wr_data[52]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[52])
// synopsys translate_off
.omni_data (omni_data[53]),
.rst (rst_l_active_high),
.rst_val (reset_addr[29]),
.csr_data (csrbus_wr_data[53]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[53])
// synopsys translate_off
.omni_data (omni_data[54]),
.rst (rst_l_active_high),
.rst_val (reset_addr[30]),
.csr_data (csrbus_wr_data[54]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[54])
// synopsys translate_off
.omni_data (omni_data[55]),
.rst (rst_l_active_high),
.rst_val (reset_addr[31]),
.csr_data (csrbus_wr_data[55]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[55])
// synopsys translate_off
.omni_data (omni_data[56]),
.rst (rst_l_active_high),
.rst_val (reset_addr[32]),
.csr_data (csrbus_wr_data[56]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[56])
// synopsys translate_off
.omni_data (omni_data[57]),
.rst (rst_l_active_high),
.rst_val (reset_addr[33]),
.csr_data (csrbus_wr_data[57]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[57])
// synopsys translate_off
.omni_data (omni_data[58]),
.rst (rst_l_active_high),
.rst_val (reset_addr[34]),
.csr_data (csrbus_wr_data[58]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[58])
// synopsys translate_off
.omni_data (omni_data[59]),
.rst (rst_l_active_high),
.rst_val (reset_addr[35]),
.csr_data (csrbus_wr_data[59]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[59])
// synopsys translate_off
.omni_data (omni_data[60]),
.rst (rst_l_active_high),
.rst_val (reset_addr[36]),
.csr_data (csrbus_wr_data[60]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[60])
// synopsys translate_off
.omni_data (omni_data[61]),
.rst (rst_l_active_high),
.rst_val (reset_addr[37]),
.csr_data (csrbus_wr_data[61]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[61])
// synopsys translate_off
.omni_data (omni_data[62]),
.rst (rst_l_active_high),
.rst_val (reset_addr[38]),
.csr_data (csrbus_wr_data[62]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[62])
// synopsys translate_off
.omni_data (omni_data[63]),
.rst (rst_l_active_high),
.rst_val (reset_addr[39]),
.csr_data (csrbus_wr_data[63]),
.q (mem_64_pcie_offset_reg_csrbus_read_data[63])
endmodule // dmu_imu_ics_csr_mem_64_pcie_offset_reg_entry