design/sys/iop/dmu/rtl/dmu_mmu_csr_tsb.v

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//
// OpenSPARC T2 Processor File: dmu_mmu_csr_tsb.v
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module dmu_mmu_csr_tsb
        (
        clk,
        rst_l,
        tsb_w_ld,
        csrbus_wr_data,
        tsb_csrbus_read_data,
        tsb_tb_hw_read,
        tsb_ps_hw_read,
        tsb_ts_hw_read
        );

//====================================================================
//     Polarity declarations
//====================================================================
input  clk;  // Clock
input  rst_l;  // Reset signal
input  tsb_w_ld;  // SW load bus
input  [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
output [`FIRE_DLC_MMU_CSR_TSB_WIDTH-1:0] tsb_csrbus_read_data;  // SW read data
output [`FIRE_DLC_MMU_CSR_TSB_TB_INT_SLC] tsb_tb_hw_read;  // This signal
                                                           // provides the
                                                           // current value of
                                                           // tsb_tb.
output tsb_ps_hw_read;  // This signal provides the current value of tsb_ps.
output [`FIRE_DLC_MMU_CSR_TSB_TS_INT_SLC] tsb_ts_hw_read;  // This signal
                                                           // provides the
                                                           // current value of
                                                           // tsb_ts.

//====================================================================
//     Type declarations
//====================================================================
wire clk;  // Clock
wire rst_l;  // Reset signal
wire tsb_w_ld;  // SW load bus
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data;  // SW write data
wire [`FIRE_DLC_MMU_CSR_TSB_WIDTH-1:0] tsb_csrbus_read_data;  // SW read data
wire [`FIRE_DLC_MMU_CSR_TSB_TB_INT_SLC] tsb_tb_hw_read;  // This signal provides
                                                         // the current value of
                                                         // tsb_tb.
wire tsb_ps_hw_read;  // This signal provides the current value of tsb_ps.
wire [`FIRE_DLC_MMU_CSR_TSB_TS_INT_SLC] tsb_ts_hw_read;  // This signal provides
                                                         // the current value of
                                                         // tsb_ts.

//====================================================================
//     Logic
//====================================================================

// synopsys translate_off
// verilint 123 off
// verilint 498 off
reg omni_ld;
reg [`FIRE_DLC_MMU_CSR_TSB_WIDTH-1:0] omni_data;

// vlint flag_unsynthesizable_initial off
initial
  begin
     omni_ld         = 1'b0;
     omni_data       = `FIRE_DLC_MMU_CSR_TSB_WIDTH'b0;
  end// vlint flag_unsynthesizable_initial on

// verilint 123 on
// verilint 498 on
// synopsys translate_on

//----- Hardware Data Out Mux Assignments
assign tsb_tb_hw_read=
           tsb_csrbus_read_data
               [`FIRE_DLC_MMU_CSR_TSB_TB_SLC];
assign tsb_ps_hw_read=
           tsb_csrbus_read_data [8];
assign tsb_ts_hw_read=
           tsb_csrbus_read_data
               [`FIRE_DLC_MMU_CSR_TSB_TS_SLC];

//====================================================================
//     Instantiation of entries
//====================================================================

//----- Entry 0
dmu_mmu_csr_tsb_entry tsb_0
        (
        // synopsys translate_off
          .omni_ld      (omni_ld),
          .omni_data    (omni_data),
        // synopsys translate_on
        .clk    (clk),
        .rst_l  (rst_l),
        .w_ld   (tsb_w_ld),
        .csrbus_wr_data (csrbus_wr_data),
        .tsb_csrbus_read_data   (tsb_csrbus_read_data)
        );

endmodule // dmu_mmu_csr_tsb