design/sys/iop/dmu/synopsys/script/user_cfg.scr

# ========== Copyright Header Begin ==========================================
#
# OpenSPARC T2 Processor File: user_cfg.scr
# Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
# 4150 Network Circle, Santa Clara, California 95054, U.S.A.
#
# * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; version 2 of the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
#
# For the avoidance of doubt, and except that if any non-GPL license
# choice is available it will apply instead, Sun elects to use only
# the General Public License version 2 (GPLv2) at this time for any
# software where a choice of GPL license versions is made
# available with the language indicating that GPLv2 or any later version
# may be used, or where a choice of which version of the GPL is applied is
# otherwise unspecified.
#
# Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
# CA 95054 USA or visit www.sun.com if you need additional information or
# have any questions.
#
# ========== Copyright Header End ============================================
source -echo -verbose $dv_root/design/sys/synopsys/script/project_io_cfg.scr

set rtl_files {\
libs/cl/cl_rtl_ext.v
libs/cl/cl_a1/cl_a1.behV
libs/cl/cl_sc1/cl_sc1.behV
libs/cl/cl_u1/cl_u1.behV
libs/cl/cl_dp1/cl_dp1.behV
libs/cl/cl_mc1/cl_mc1.v

libs/clk/rtl/clkgen_dmu_io.v

libs/n2sram/dp/n2_dmu_dp_144x149s_cust_l/n2_dmu_dp_144x149s_cust/rtl/n2_dmu_dp_144x149s_cust.v
libs/n2sram/dp/n2_dmu_dp_128x132s_cust_l/n2_dmu_dp_128x132s_cust/rtl/n2_dmu_dp_128x132s_cust.v
libs/n2sram/dp/n2_dmu_dp_512x60s_cust_l/n2_dmu_dp_512x60s_cust/rtl/n2_dmu_dp_512x60s_cust.v
libs/n2sram/compiler/physical/n2_com_dp_16x132s_cust_l/n2_com_dp_16x132s_cust/rtl/n2_com_dp_16x132s_cust.v
libs/n2sram/cams/n2_mmu_cm_64x34s_cust_l/n2_mmu_cm_64x34s_cust/rtl/n2_mmu_cm_64x34s_cust.v

libs/n2sram/sp/n2_iom_sp_devtsb_cust_l/n2_iom_sp_devtsb_cust/rtl/n2_iom_sp_devtsb_cust.v
libs/clk/n2_clk_pgrid_cust_l/n2_clk_dmu_io_cust/rtl/n2_clk_dmu_io_cust.v
libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v

design/sys/iop/dmu/rtl/dmu.h
design/sys/iop/dmu/rtl/dmu_clu.h
design/sys/iop/dmu/rtl/dmu_cmu.h
design/sys/iop/dmu/rtl/dmu_imu.h
design/sys/iop/dmu/rtl/dmu_mmu.h
design/sys/iop/dmu/rtl/dmu_pmu.h
design/sys/iop/dmu/rtl/dmu_rmu.h

design/sys/iop/dmu/rtl/dmu_imu_iss_defines.h
design/sys/iop/dmu/rtl/dmu_imu_eqs_defines.h
design/sys/iop/dmu/rtl/dmu_imu_rds_intx_defines.h
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_defines.h
design/sys/iop/dmu/rtl/dmu_imu_rds_msi_defines.h
design/sys/iop/dmu/rtl/dmu_imu_ics_defines.h
design/sys/iop/dmu/rtl/dmu_mmu_csr_defines.h
design/sys/iop/dmu/rtl/dmu_ilu_cib_defines.h
design/sys/iop/dmu/rtl/dmu_cru_defines.h
design/sys/iop/dmu/rtl/dmu_psb_defines.h
design/sys/iop/dmu/rtl/dmu_tsb_defines.h

design/sys/iop/pcie_common/rtl/pcie.h
design/sys/iop/pcie_common/rtl/pcie_csr_defines.h
design/sys/iop/pcie_common/rtl/dmu_csrtool_enable_all.h
design/sys/iop/pcie_common/rtl/dmu_csrtool_enable_none.h
design/sys/iop/pcie_common/rtl/dmu_pathto_defines.h
design/sys/iop/pcie_common/rtl/dmu_user_defines.h

design/sys/iop/dmu/rtl/dmu_cb0.v
design/sys/iop/dmu/rtl/dmu_clu.v
design/sys/iop/dmu/rtl/dmu_clu_crm.v
design/sys/iop/dmu/rtl/dmu_clu_crm_arb.v
design/sys/iop/dmu/rtl/dmu_clu_crm_datactl.v
design/sys/iop/dmu/rtl/dmu_clu_crm_datapipe.v
design/sys/iop/dmu/rtl/dmu_clu_crm_pktctlfsm.v
design/sys/iop/dmu/rtl/dmu_clu_crm_pktgen.v
design/sys/iop/dmu/rtl/dmu_clu_crm_psbctlfsm.v
design/sys/iop/dmu/rtl/dmu_clu_ctm.v
design/sys/iop/dmu/rtl/dmu_clu_ctm_bufmgr.v
design/sys/iop/dmu/rtl/dmu_clu_ctm_cmdctlfsm.v
design/sys/iop/dmu/rtl/dmu_clu_ctm_cmdgen.v
design/sys/iop/dmu/rtl/dmu_clu_ctm_datactlfsm.v
design/sys/iop/dmu/rtl/dmu_clu_ctm_datapipe.v
design/sys/iop/dmu/rtl/dmu_clu_ctm_tagmgr.v
design/sys/iop/dmu/rtl/dmu_clu_debug.v
design/sys/iop/dmu/rtl/dmu_cmu.v
design/sys/iop/dmu/rtl/dmu_cmu_clst_aloc.v
design/sys/iop/dmu/rtl/dmu_cmu_ctx.v
design/sys/iop/dmu/rtl/dmu_cmu_ctx_aloc.v
design/sys/iop/dmu/rtl/dmu_cmu_ctx_clstreg_array.v
design/sys/iop/dmu/rtl/dmu_cmu_ctx_pkseqaloc.v
design/sys/iop/dmu/rtl/dmu_cmu_ctx_reg_array.v
design/sys/iop/dmu/rtl/dmu_cmu_dbg.v
design/sys/iop/dmu/rtl/dmu_cmu_rcm.v
design/sys/iop/dmu/rtl/dmu_cmu_rcm_schrcd_q.v
design/sys/iop/dmu/rtl/dmu_cmu_tcm.v
design/sys/iop/dmu/rtl/dmu_cmu_tcm_pkrcd_q.v
design/sys/iop/dmu/rtl/dmu_cru.v
design/sys/iop/dmu/rtl/dmu_cru_addr_decode.v
design/sys/iop/dmu/rtl/dmu_cru_csr.v
design/sys/iop/dmu/rtl/dmu_cru_csr_dmc_dbg_sel_a_reg.v
design/sys/iop/dmu/rtl/dmu_cru_csr_dmc_dbg_sel_a_reg_entry.v
design/sys/iop/dmu/rtl/dmu_cru_csr_dmc_dbg_sel_b_reg.v
design/sys/iop/dmu/rtl/dmu_cru_csr_dmc_dbg_sel_b_reg_entry.v
design/sys/iop/dmu/rtl/dmu_cru_csr_dmc_pcie_cfg.v
design/sys/iop/dmu/rtl/dmu_cru_csr_dmc_pcie_cfg_entry.v
design/sys/iop/dmu/rtl/dmu_cru_csrpipe_3.v
design/sys/iop/dmu/rtl/dmu_cru_csrpipe_5.v
design/sys/iop/dmu/rtl/dmu_cru_default_grp.v
design/sys/iop/dmu/rtl/dmu_cru_stage_mux_only.v
design/sys/iop/dmu/rtl/dmu_diu.v
design/sys/iop/dmu/rtl/dmu_diu_idm.v
design/sys/iop/dmu/rtl/dmu_diu_idr.v
design/sys/iop/dmu/rtl/dmu_dou.v
design/sys/iop/dmu/rtl/dmu_dou_edr.v
design/sys/iop/dmu/rtl/dmu_dou_epr.v
design/sys/iop/dmu/rtl/dmu_dsn.v
design/sys/iop/dmu/rtl/dmu_dsn_ccc_dep.v
design/sys/iop/dmu/rtl/dmu_dsn_ccc_fsm.v
design/sys/iop/dmu/rtl/dmu_dsn_ccc_pkt.v
design/sys/iop/dmu/rtl/dmu_dsn_ctl.v
design/sys/iop/dmu/rtl/dmu_dsn_mondo_fifo.v
design/sys/iop/dmu/rtl/dmu_dsn_ucb_flow.v
design/sys/iop/dmu/rtl/dmu_dsn_ucb_in32.v
design/sys/iop/dmu/rtl/dmu_dsn_ucb_out32.v
design/sys/iop/dmu/rtl/dmu_imu.v
design/sys/iop/dmu/rtl/dmu_imu_dbg.v
design/sys/iop/dmu/rtl/dmu_imu_dms.v
design/sys/iop/dmu/rtl/dmu_imu_eqs.v
design/sys/iop/dmu/rtl/dmu_imu_eqs_addr_decode.v
design/sys/iop/dmu/rtl/dmu_imu_eqs_csr.v
design/sys/iop/dmu/rtl/dmu_imu_eqs_csr_eq_base_address.v
design/sys/iop/dmu/rtl/dmu_imu_eqs_csr_eq_base_address_entry.v
design/sys/iop/dmu/rtl/dmu_imu_eqs_csr_eq_head.v
design/sys/iop/dmu/rtl/dmu_imu_eqs_csr_eq_head_entry.v
design/sys/iop/dmu/rtl/dmu_imu_eqs_csr_eq_tail.v
design/sys/iop/dmu/rtl/dmu_imu_eqs_csr_eq_tail_entry.v
design/sys/iop/dmu/rtl/dmu_imu_eqs_csrpipe_109.v
design/sys/iop/dmu/rtl/dmu_imu_eqs_csrpipe_5.v
design/sys/iop/dmu/rtl/dmu_imu_eqs_default_grp.v
design/sys/iop/dmu/rtl/dmu_imu_eqs_fsm.v
design/sys/iop/dmu/rtl/dmu_imu_eqs_stage_mux_only.v
design/sys/iop/dmu/rtl/dmu_imu_gcs.v
design/sys/iop/dmu/rtl/dmu_imu_gcs_arb.v
design/sys/iop/dmu/rtl/dmu_imu_gcs_csm.v
design/sys/iop/dmu/rtl/dmu_imu_gcs_gc.v
design/sys/iop/dmu/rtl/dmu_imu_gcs_gc_cnt.v
design/sys/iop/dmu/rtl/dmu_imu_gcs_gc_fsm.v
design/sys/iop/dmu/rtl/dmu_imu_ics.v
design/sys/iop/dmu/rtl/dmu_imu_ics_addr_decode.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_dmc_interrupt_mask_reg.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_dmc_interrupt_mask_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_eqs_error_log_reg.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_eqs_error_log_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_error_log_en_reg.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_error_log_en_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_int_en_reg.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_int_en_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_logged_error_status_reg.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_logged_error_status_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_perf_cnt0.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_perf_cnt0_entry.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_perf_cnt1.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_perf_cnt1_entry.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_perf_cntrl.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_perf_cntrl_entry.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_rds_error_log_reg.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_rds_error_log_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_scs_error_log_reg.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_imu_scs_error_log_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_mem_64_pcie_offset_reg.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_mem_64_pcie_offset_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_msi_32_addr_reg.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_msi_32_addr_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_msi_64_addr_reg.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csr_msi_64_addr_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csrpipe_15.v
design/sys/iop/dmu/rtl/dmu_imu_ics_csrpipe_5.v
design/sys/iop/dmu/rtl/dmu_imu_ics_default_grp.v
design/sys/iop/dmu/rtl/dmu_imu_ics_stage_mux_only.v
design/sys/iop/dmu/rtl/dmu_imu_irs.v
design/sys/iop/dmu/rtl/dmu_imu_iss.v
design/sys/iop/dmu/rtl/dmu_imu_iss_addr_decode.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_20.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_20_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_21.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_21_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_22.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_22_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_23.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_23_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_24.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_24_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_25.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_25_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_26.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_26_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_27.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_27_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_28.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_28_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_29.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_29_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_30.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_30_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_31.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_31_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_32.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_32_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_33.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_33_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_34.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_34_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_35.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_35_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_36.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_36_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_37.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_37_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_38.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_38_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_39.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_39_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_40.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_40_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_41.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_41_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_42.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_42_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_43.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_43_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_44.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_44_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_45.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_45_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_46.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_46_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_47.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_47_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_48.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_48_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_49.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_49_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_50.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_50_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_51.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_51_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_52.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_52_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_53.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_53_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_54.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_54_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_55.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_55_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_56.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_56_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_57.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_57_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_58.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_58_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_59.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_59_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_62.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_62_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_63.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_mapping_63_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_retry_timer.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csr_interrupt_retry_timer_entry.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csrpipe_5.v
design/sys/iop/dmu/rtl/dmu_imu_iss_csrpipe_87.v
design/sys/iop/dmu/rtl/dmu_imu_iss_default_grp.v
design/sys/iop/dmu/rtl/dmu_imu_iss_fsm.v
design/sys/iop/dmu/rtl/dmu_imu_iss_stage_mux_only.v
design/sys/iop/dmu/rtl/dmu_imu_ors.v
design/sys/iop/dmu/rtl/dmu_imu_rds.v
design/sys/iop/dmu/rtl/dmu_imu_rds_intx.v
design/sys/iop/dmu/rtl/dmu_imu_rds_intx_addr_decode.v
design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr.v
design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_a_int_clr_reg.v
design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_a_int_clr_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_b_int_clr_reg.v
design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_b_int_clr_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_c_int_clr_reg.v
design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_c_int_clr_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_d_int_clr_reg.v
design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csr_int_d_int_clr_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csrpipe_1.v
design/sys/iop/dmu/rtl/dmu_imu_rds_intx_csrpipe_5.v
design/sys/iop/dmu/rtl/dmu_imu_rds_intx_default_grp.v
design/sys/iop/dmu/rtl/dmu_imu_rds_intx_stage_mux_only.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_addr_decode.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_err_cor_mapping.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_err_cor_mapping_entry.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_err_fatal_mapping.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_err_fatal_mapping_entry.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_err_nonfatal_mapping.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_err_nonfatal_mapping_entry.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_pm_pme_mapping.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_pm_pme_mapping_entry.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_pme_to_ack_mapping.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csr_pme_to_ack_mapping_entry.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csrpipe_1.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_csrpipe_6.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_default_grp.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mess_stage_mux_only.v
design/sys/iop/dmu/rtl/dmu_imu_rds_mondo.v
design/sys/iop/dmu/rtl/dmu_imu_rds_msi.v
design/sys/iop/dmu/rtl/dmu_imu_rds_msi_addr_decode.v
design/sys/iop/dmu/rtl/dmu_imu_rds_msi_csr.v
design/sys/iop/dmu/rtl/dmu_imu_rds_msi_csr_int_mondo_data_0_reg.v
design/sys/iop/dmu/rtl/dmu_imu_rds_msi_csr_int_mondo_data_0_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_rds_msi_csr_int_mondo_data_1_reg.v
design/sys/iop/dmu/rtl/dmu_imu_rds_msi_csr_int_mondo_data_1_reg_entry.v
design/sys/iop/dmu/rtl/dmu_imu_rds_msi_csrpipe_1.v
design/sys/iop/dmu/rtl/dmu_imu_rds_msi_csrpipe_3.v
design/sys/iop/dmu/rtl/dmu_imu_rds_msi_default_grp.v
design/sys/iop/dmu/rtl/dmu_imu_rds_msi_stage_2_default_grp.v
design/sys/iop/dmu/rtl/dmu_imu_rds_msi_stage_mux_only.v
design/sys/iop/dmu/rtl/dmu_imu_rss.v
design/sys/iop/dmu/rtl/dmu_imu_scs.v

design/sys/iop/dmu/rtl/dmu_mb0.v
design/sys/iop/dmu/rtl/dmu_pmu.v
design/sys/iop/dmu/rtl/dmu_pmu_prcd_q.v
design/sys/iop/dmu/rtl/dmu_pmu_prm.v
design/sys/iop/dmu/rtl/dmu_psb.v
design/sys/iop/dmu/rtl/dmu_psb_addr_decode.v
design/sys/iop/dmu/rtl/dmu_psb_csr.v
design/sys/iop/dmu/rtl/dmu_psb_csrpipe_1.v
design/sys/iop/dmu/rtl/dmu_psb_csrpipe_2.v
design/sys/iop/dmu/rtl/dmu_psb_dbg.v
design/sys/iop/dmu/rtl/dmu_psb_default_grp.v
design/sys/iop/dmu/rtl/dmu_psb_pdl.v
design/sys/iop/dmu/rtl/dmu_psb_ptg.v
design/sys/iop/dmu/rtl/dmu_psb_stage_mux_only.v
design/sys/iop/dmu/rtl/dmu_rmu.v
design/sys/iop/dmu/rtl/dmu_rmu_dbg.v
design/sys/iop/dmu/rtl/dmu_rmu_lrm.v
design/sys/iop/dmu/rtl/dmu_rmu_lrm_ictl.v
design/sys/iop/dmu/rtl/dmu_rmu_lrm_itsb_fsm.v
design/sys/iop/dmu/rtl/dmu_rmu_lrm_octl.v
design/sys/iop/dmu/rtl/dmu_rmu_rrm.v
design/sys/iop/dmu/rtl/dmu_rmu_rrm_efsm.v
design/sys/iop/dmu/rtl/dmu_rmu_rrm_erel.v
design/sys/iop/dmu/rtl/dmu_rmu_rrm_etsbfsm.v
design/sys/iop/dmu/rtl/dmu_tmu.v
design/sys/iop/dmu/rtl/dmu_tmu_dim.v
design/sys/iop/dmu/rtl/dmu_tmu_dim_bufmgr.v
design/sys/iop/dmu/rtl/dmu_tmu_dim_datafsm.v
design/sys/iop/dmu/rtl/dmu_tmu_dim_datapath.v
design/sys/iop/dmu/rtl/dmu_tmu_dim_rcdbldr.v
design/sys/iop/dmu/rtl/dmu_tmu_dim_relgen.v
design/sys/iop/dmu/rtl/dmu_tmu_dim_xfrfsm.v
design/sys/iop/dmu/rtl/dmu_tsb.v
design/sys/iop/dmu/rtl/dmu_tsb_csr.v
design/sys/iop/dmu/rtl/dmu_tsb_dbg.v
design/sys/iop/dmu/rtl/dmu_tsb_tdl.v
design/sys/iop/dmu/rtl/dmu_tsb_ttg.v
design/sys/iop/dmu/rtl/dmu_mmu.v
design/sys/iop/dmu/rtl/dmu_mmu_arbiter_rrobin.v
design/sys/iop/dmu/rtl/dmu_mmu_crb.v
design/sys/iop/dmu/rtl/dmu_mmu_csr.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_addr_decode.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_cim.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_csr.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_csrpipe_1.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_csrpipe_15.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_ctl.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_ctl_entry.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_default_grp.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_err.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_err_entry.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_flta.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_flta_entry.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_flts.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_flts_entry.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_fsh.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_fsh_entry.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_int_en.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_int_en_entry.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_log.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_log_entry.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_prf0.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_prf0_entry.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_prf1.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_prf1_entry.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_prfc.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_prfc_entry.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_stage_2_default_grp.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_stage_mux_only.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_tsb.v
design/sys/iop/dmu/rtl/dmu_mmu_csr_tsb_entry.v
design/sys/iop/dmu/rtl/dmu_mmu_irb.v
design/sys/iop/dmu/rtl/dmu_mmu_orb.v
design/sys/iop/dmu/rtl/dmu_mmu_pab.v
design/sys/iop/dmu/rtl/dmu_mmu_ptb.v
design/sys/iop/dmu/rtl/dmu_mmu_qcb.v
design/sys/iop/dmu/rtl/dmu_mmu_qcb_qgc.v
design/sys/iop/dmu/rtl/dmu_mmu_qcb_qmc.v
design/sys/iop/dmu/rtl/dmu_mmu_rcb.v
design/sys/iop/dmu/rtl/dmu_mmu_srq.v
design/sys/iop/dmu/rtl/dmu_mmu_srq_iommu.v
design/sys/iop/dmu/rtl/dmu_mmu_tcb.v
design/sys/iop/dmu/rtl/dmu_mmu_tcb_tcc.v
design/sys/iop/dmu/rtl/dmu_mmu_tcb_tdc.v
design/sys/iop/dmu/rtl/dmu_mmu_tcb_tmc.v
design/sys/iop/dmu/rtl/dmu_mmu_tdb.v
design/sys/iop/dmu/rtl/dmu_mmu_tlb.v
design/sys/iop/dmu/rtl/dmu_mmu_vab.v
design/sys/iop/dmu/rtl/dmu_mmu_vtb.v
design/sys/iop/dmu/rtl/dmu_ilu.v
design/sys/iop/dmu/rtl/dmu_ilu_cib.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_addr_decode.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_cim.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_csr.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_diagnos.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_diagnos_entry.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_int_en.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_int_en_entry.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_en.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_en_entry.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_err.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_err_entry.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_pec_int_en.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_pec_int_en_entry.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_csrpipe_5.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_csrpipe_6.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_default_grp.v
design/sys/iop/dmu/rtl/dmu_ilu_cib_stage_mux_only.v
design/sys/iop/dmu/rtl/dmu_ilu_eil.v
design/sys/iop/dmu/rtl/dmu_ilu_eil_bufmgr.v
design/sys/iop/dmu/rtl/dmu_ilu_eil_datafsm.v
design/sys/iop/dmu/rtl/dmu_ilu_eil_rcdbldr.v
design/sys/iop/dmu/rtl/dmu_ilu_eil_relgen.v
design/sys/iop/dmu/rtl/dmu_ilu_eil_xfrfsm.v
design/sys/iop/dmu/rtl/dmu_ilu_iil.v
design/sys/iop/dmu/rtl/dmu_ilu_iil_bufmgr.v
design/sys/iop/dmu/rtl/dmu_ilu_iil_crdtcnt.v
design/sys/iop/dmu/rtl/dmu_ilu_iil_parchk.v
design/sys/iop/dmu/rtl/dmu_ilu_iil_rcdbldr.v
design/sys/iop/dmu/rtl/dmu_ilu_iil_xfrfsm.v
design/sys/iop/dmu/rtl/dmu_ilu_isb.v
design/sys/iop/pcie_common/rtl/csr_sw.v
design/sys/iop/pcie_common/rtl/dmu_common_ccc.v
design/sys/iop/pcie_common/rtl/dmu_common_ccc_arb.v
design/sys/iop/pcie_common/rtl/dmu_common_ccc_cdp.v
design/sys/iop/pcie_common/rtl/dmu_common_ccc_dep.v
design/sys/iop/pcie_common/rtl/dmu_common_ccc_fsm.v
design/sys/iop/pcie_common/rtl/dmu_common_ccc_pkt.v
design/sys/iop/pcie_common/rtl/pcie_common_dcb.v
design/sys/iop/pcie_common/rtl/pcie_common_dcc.v
design/sys/iop/pcie_common/rtl/pcie_common_dcd.v
design/sys/iop/pcie_common/rtl/pcie_common_dcs.v
design/sys/iop/pcie_common/rtl/pcie_common_dcs_ism.v
design/sys/iop/pcie_common/rtl/pcie_common_dcs_osm.v
design/sys/iop/pcie_common/rtl/pcie_common_dcs_sdp.v
design/sys/iop/pcie_common/rtl/pcie_dcm_daemon.v
design/sys/iop/pcie_common/rtl/pcie_common_frr_arbiter.v
design/sys/iop/pcie_common/rtl/dmu_common_scoreboard_controller.v
design/sys/iop/pcie_common/rtl/fire_dmc_common_srfifo.v
design/sys/iop/pcie_common/rtl/dmu_common_simple_fifo.v
design/sys/iop/pcie_common/rtl/pcie_common_srq.v
design/sys/iop/pcie_common/rtl/pcie_common_srq_qci.v
design/sys/iop/pcie_common/rtl/pcie_common_srq_qcp.v
design/sys/iop/pcie_common/rtl/pcie_common_srq_qdp.v
design/sys/iop/pcie_common/rtl/pcie_common_sync_flop.v

design/sys/iop/dmu/rtl/dmu_dmc.v
design/sys/iop/dmu/rtl/dmu.v
}

set link_library [concat $link_library \
   dw_foundation.sldb \
]


set mix_files {}
set top_module dmu

set include_paths {\
design/sys/iop/pcie_common/rtl \
design/sys/iop/dmu/rtl \
}

set black_box_libs {}
set black_box_designs {}
set mem_libs {}

set dont_touch_modules {\
n2_com_dp_16x132s_cust \
n2_dmu_dp_128x132s_cust \
n2_dmu_dp_144x149s_cust \
n2_dmu_dp_512x60s_cust \
n2_mmu_cm_64x34s_cust \
n2_iom_sp_devtsb_cust \
n2_clk_clstr_hdr_cust \
n2_clk_dmu_io_cust \
}

set compile_effort   "medium"

set compile_flatten_all 1

set compile_no_new_cells_at_top_level false

set default_clk gclk
set default_clk_freq  350
set default_setup_skew  0.0
set default_hold_skew  0.0
set default_clk_transition  0.05
set clk_list {                        \
                { gclk    350.0   0.000   0.000   0.05}        \
}

set ideal_net_list {}
set false_path_list {}
set enforce_input_fanout_one     0
set allow_outport_drive_innodes  1
set skip_scan            0
set add_lockup_latch     false
set chain_count          1
set scanin_port_list     {}
set scanout_port_list    {}
set scanenable_port      global_shift_enable
set has_test_stub        1
set scanenable_pin       test_stub_no_bist/se
set long_chain_so_0_net  long_chain_so_0
set short_chain_so_0_net short_chain_so_0
set so_0_net             so_0
set insert_extra_lockup_latch 0
set extra_lockup_latch_clk_list {}