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// OpenSPARC T2 Processor File: l2t_dirbuf_ctl.v
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dirlbf_inval_mask_c4_buf,
dirlbf_lkup_wr_data_c4_buf,
wire ff_l2t_mb0_run_r1_scanin;
wire ff_l2t_mb0_run_r1_scanout;
wire dirlbf_force_hit_c41;
wire l2t_mb0_row_wr_en_qual;
wire l2t_mb0_row_rd_en_qual;
wire [3:0] dirlbf_rw_dec_c4_buf_fnl;
wire [3:0] dirlbf_lkup_en_c4_buf_fnl;
input [7:0] dir_inval_mask_c4;
input [1:0] rw_row_en_c4;
input [3:0] rw_panel_en_c4;
input [5:0] dir_rw_entry_c4; // BS and SR 11/18/03 Reverse Directory change
input [1:0] lkup_row_en_c4; // qualified already
input [3:0] lkup_panel_en_c4; // qualified already
input [14:0] lkup_wr_data_c4; // BS and SR 11/18/03 Reverse Directory change
input arbadr_arbdp_addr4_c4;
input [7:0] l2t_mb0_mask;
input [5:0] l2t_mb0_addr;
input [3:0] l2t_mb0_row_panel_en;
input l2t_mb0_row_row_en;
input [3:0] l2t_mb0_row_lookup_en;
input [15:0] l2t_mb0_lookup_wdata;
output dirlbf_force_hit_c4;
output [3:0] dirlbf_lkup_en_c4_buf ;
output [7:0] dirlbf_inval_mask_c4_buf ;
output [3:0] dirlbf_rw_dec_c4_buf;
output dirlbf_rd_en_c4_buf ;
output dirlbf_wr_en_c4_buf ;
output [5:0] dirlbf_rw_entry_c4_buf; // BS and SR 11/18/03 Reverse Directory change
output [15:0] dirlbf_lkup_wr_data_c4_buf; // 14(top) to 0(bottom)
output dirlbf_dir_clear_c4_buf;
// Muxing of MBIST and functional signals
l2t_dirbuf_ctl_msff_ctl_macro__width_1 ff_l2t_mb0_run_r1
.scan_in(ff_l2t_mb0_run_r1_scanin),
.scan_out(ff_l2t_mb0_run_r1_scanout),
l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_mb0_row_row_en_wdata
.dout ({dirlbf_force_hit_c4,mb0_row_row_en}),
.din0 ({1'b0,l2t_mb0_row_row_en}),
.din1 ({dirlbf_force_hit_c41,1'b0}),
l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_8 mux_dirlbf_inval_mask_c4_buf
.dout (dirlbf_inval_mask_c4_buf[7:0]),
.din0 (dir_inval_mask_c4[7:0]),
.din1 (l2t_mb0_mask[7:0]),
l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_6 mux_rw_index
.din0 ({addr_index_bit5,dir_rw_entry_c4[4:0]}),
.din1 (dir_rw_entry_c4[5:0]),
.sel0 (~dirlbf_wr_en_c4_buf),
.sel1 (dirlbf_wr_en_c4_buf)
assign l2t_mb0_row_wr_en_qual = l2t_mb0_row_wr_en & l2t_mb0_row_row_en;
assign l2t_mb0_row_rd_en_qual = l2t_mb0_row_rd_en & l2t_mb0_row_row_en;
l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_8 mux_dirlbf_rd_wr_entry_c4_buf
.dout ({dirlbf_rw_entry_c4_buf[5:0],dirlbf_wr_en_c4_buf,dirlbf_rd_en_c4_buf}),
.din0 ({rw_index[5:0],wr_en_c4,rd_en_c4}),
.din1 ({l2t_mb0_addr[5:0],l2t_mb0_row_wr_en_qual,l2t_mb0_row_rd_en_qual}),
assign address_bit4_0 = ~(ic_address_bit4 & ic_dc_dir);
assign address_bit4_1 = ~(dc_address_bit4 & ~ic_dc_dir);
assign address_bit4 = ~(address_bit4_0 & address_bit4_1);
assign dirlbf_force_hit_c41 = arb_force_hit_c4 | (lkup_row_en_c4[0] & lkup_row_en_c4[1]);
assign sel_address_bit4 = (dirlbf_wr_en_c4_buf | dirlbf_rd_en_c4_buf);
l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_2 mux_address_bit4
.dout ({dc_address_bit4,ic_address_bit4}),
.din0 ({dir_rw_entry_c4[5],dir_rw_entry_c4[5]}),
.din1 ({lkup_row_en_c4[1],arbadr_arbdp_addr4_c4}),
.sel0 (sel_address_bit4),
.sel1 (~sel_address_bit4)
//prty_macro prty_dir_wr_par_c4 (width=16)
// .dout (dir_wr_par_c4),
// .din ({1'b0,address_bit4,lkup_wr_data_c4[13:0]})
assign dir_wr_par_c4 = ^(lkup_wr_data_c4[13:0]) ^ address_bit4;
l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_16 mux_dirlbf_lkup_wr_data_c4_buf
.dout (dirlbf_lkup_wr_data_c4_buf[15:0]),
.din0 ({lkup_wr_data_c4[14],dir_wr_par_c4,address_bit4,lkup_wr_data_c4[12:0]}),
.din1 (l2t_mb0_lookup_wdata[15:0]),
assign cam_row_select = |(lkup_row_en_c4[1:0]);
assign rw_row_select = ((|(rw_row_en_c4[1:0])) | mb0_row_row_en);
assign dirlbf_dir_clear_c4_buf = dir_clear_c4;
assign dirlbf_rw_dec_c4_buf_fnl[3:0] = rw_panel_en_c4[3:0] & {4{rw_row_select}};
l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_dirlbf_rw_dec_c4_buf
.dout (dirlbf_rw_dec_c4_buf[3:0]),
.din0 (dirlbf_rw_dec_c4_buf_fnl[3:0]),
.din1 (l2t_mb0_row_panel_en),
assign dirlbf_lkup_en_c4_buf_fnl[3:0] = lkup_panel_en_c4[3:0] & {4{cam_row_select}};
//assign mbist_lookup_en[3:0] = l2t_mb0_row_lookup_en[3:0] & {4{l2t_mb0_row_row_en}};
l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 mux_dirlbf_lkup_en_c4_buf
.dout (dirlbf_lkup_en_c4_buf[3:0]),
.din0 (dirlbf_lkup_en_c4_buf_fnl[3:0]),
.din1 (l2t_mb0_row_lookup_en[3:0]),
assign ff_l2t_mb0_run_r1_scanin = scan_in ;
assign scan_out = ff_l2t_mb0_run_r1_scanout;
// any PARAMS parms go into naming of macro
module l2t_dirbuf_ctl_msff_ctl_macro__width_1 (
assign fdin[0:0] = din[0:0];
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_2 (
assign dout[1:0] = ( {2{sel0}} & din0[1:0] ) |
( {2{sel1}} & din1[1:0]);
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_8 (
assign dout[7:0] = ( {8{sel0}} & din0[7:0] ) |
( {8{sel1}} & din1[7:0]);
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_6 (
assign dout[5:0] = ( {6{sel0}} & din0[5:0] ) |
( {6{sel1}} & din1[5:0]);
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_16 (
assign dout[15:0] = ( {16{sel0}} & din0[15:0] ) |
( {16{sel1}} & din1[15:0]);
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_dirbuf_ctl_mux_ctl_macro__mux_aonpe__ports_2__width_4 (
assign dout[3:0] = ( {4{sel0}} & din0[3:0] ) |
( {4{sel1}} & din1[3:0]);