// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: l2t_ecc30b_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
output [4:0] corrected_bit ;
wire [4:0] corrected_bit ;
//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
// |1 |2 |3 |4 |5 |6 |7 |8 |9 |10|11|12|13|14|15 |16 |17 |18 |19 |20 |21 |22 |23 |24 |25 |26 |27 |28 |29 |30 |
// |P1|P2|D0|P4|D1|D2|D3|P8|D4|D5|D6|D7|D8|D9|D10|P16|D11|D12|D13|D14|D15|D16|D17|D18|D19|D20|D21|D22|D23|P30|
//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
//P1 |* | |* | |* | |* | |* | |* | |* | | * | | * | | * | | * | | * | | * | | * | | * | |
//P2 | |* |* | | |* |* | | |* |* | | |* | * | | | * | * | | | * | * | | | * | * | | | |
//P4 | | | |* |* |* |* | | | | |* |* |* | * | | | | | * | * | * | * | | | | | * | * | |
//P8 | | | | | | | |* |* |* |* |* |* |* | * | | | | | | | | | * | * | * | * | * | * | |
//P16 | | | | | | | | | | | | | | | | * | * | * | * | * | * | * | * | * | * | * | * | * | * | |
//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
//p30 |* |* |* |* |* |* |* |* |* |* |* |* |* |* | * | * | * | * | * | * | * | * | * | * | * | * | * | * | * | * |
//----|--|--|--|--|--|--|--|--|--|--|--|--|--|--|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
//assign p1 = parity[0] ^
// din[0] ^ din[1] ^ din[3] ^ din[4] ^ din[6] ^ din[8] ^
// din[10] ^ din[11] ^ din[13] ^ din[15] ^ din[17] ^ din[19] ^
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p1_slice_10 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p1_slice_11 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p1_slice_12 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p1_slice_13 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p1_slice_14 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p1_slice_20 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p1_slice (
//assign p2 = parity[1] ^
// din[0] ^ din[2] ^ din[3] ^ din[5] ^ din[6] ^ din[9] ^
// din[10] ^ din[12] ^ din[13] ^ din[16] ^ din[17] ^ din[20] ^
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p2_slice_10 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p2_slice_11 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p2_slice_12 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p2_slice_13 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p2_slice_20 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p2_slice_21 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_2__width_1 p2_slice (
//assign p4 = parity[2] ^
// din[1] ^ din[2] ^ din[3] ^ din[7] ^ din[8] ^ din[9] ^
// din[10] ^ din[14] ^ din[15] ^ din[16] ^ din[17] ^ din[22] ^
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p4_slice_10 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p4_slice_11 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p4_slice_12 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p4_slice_13 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p4_slice_20 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p4_slice_21 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_2__width_1 p4_slice (
//assign p8 = parity[3] ^
// din[4] ^ din[5] ^ din[6] ^ din[7] ^ din[8] ^ din[9] ^
// din[10] ^ din[18] ^ din[19] ^ din[20] ^ din[21] ^ din[22] ^
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p8_slice_10 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p8_slice_11 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p8_slice_12 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p8_slice_13 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p8_slice_20 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p8_slice_21 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_2__width_1 p8_slice (
//assign p16 = parity[4] ^
// din[11] ^ din[12] ^ din[13] ^ din[14] ^ din[15] ^ din[16] ^
// din[17] ^ din[18] ^ din[19] ^ din[20] ^ din[21] ^ din[22] ^
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p16_slice_10 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p16_slice_11 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p16_slice_12 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p16_slice_13 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p16_slice_20 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 p16_slice_21 (
l2t_ecc30b_dp_xor_macro__dxor_8x__ports_2__width_1 p16_slice (
//assign error_bit[0] = !p16 & !p8 & !p4 & p2 & p1 ; // 3
//assign error_bit[1] = !p16 & !p8 & p4 & !p2 & p1 ; // 5
//assign error_bit[2] = !p16 & !p8 & p4 & p2 & !p1 ; // 6
//assign error_bit[3] = !p16 & !p8 & p4 & p2 & p1 ; // 7
//assign error_bit[4] = !p16 & p8 & !p4 & !p2 & p1 ; // 9
//assign error_bit[5] = !p16 & p8 & !p4 & p2 & !p1 ; // 10
//assign error_bit[6] = !p16 & p8 & !p4 & p2 & p1 ; // 11
//assign error_bit[7] = !p16 & p8 & p4 & !p2 & !p1 ; // 12
//assign error_bit[8] = !p16 & p8 & p4 & !p2 & p1 ; // 13
//assign error_bit[9] = !p16 & p8 & p4 & p2 & !p1 ; // 14
//assign error_bit[10] = !p16 & p8 & p4 & p2 & p1 ; // 15
//assign error_bit[11] = p16 & !p8 & !p4 & !p2 & p1 ; // 17
//assign error_bit[12] = p16 & !p8 & !p4 & p2 & !p1 ; // 18
//assign error_bit[13] = p16 & !p8 & !p4 & p2 & p1 ; // 19
//assign error_bit[14] = p16 & !p8 & p4 & !p2 & !p1 ; // 20
//assign error_bit[15] = p16 & !p8 & p4 & !p2 & p1 ; // 21
//assign error_bit[16] = p16 & !p8 & p4 & p2 & !p1 ; // 22
//assign error_bit[17] = p16 & !p8 & p4 & p2 & p1 ; // 23
//assign error_bit[18] = p16 & p8 & !p4 & !p2 & !p1 ; // 24
//assign error_bit[19] = p16 & p8 & !p4 & !p2 & p1 ; // 25
//assign error_bit[20] = p16 & p8 & !p4 & p2 & !p1 ; // 26
//assign error_bit[21] = p16 & p8 & !p4 & p2 & p1 ; // 27
//assign error_bit[22] = p16 & p8 & p4 & !p2 & !p1 ; // 28
//assign error_bit[23] = p16 & p8 & p4 & !p2 & p1 ; // 29
l2t_ecc30b_dp_inv_macro__stack_1r__width_1 p1_inv_slice
l2t_ecc30b_dp_inv_macro__stack_1r__width_1 c2_inv_slice
l2t_ecc30b_dp_inv_macro__stack_1r__width_1 p3_inv_slice
l2t_ecc30b_dp_inv_macro__stack_1r__width_1 p4_inv_slice
l2t_ecc30b_dp_inv_macro__stack_1r__width_1 p5_inv_slice
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit0_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit0_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit0_slice_10c (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit0_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit0_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit1_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit1_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit1_slice_10c (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit1_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit1_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit2_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit2_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit2_slice_10c (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit2_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit2_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit3_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit3_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit3_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit3_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit4_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit4_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit4_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit4_slice_11b (
/////////////////////////
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit5_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit5_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit5_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit5_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit6_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit6_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit6_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit6_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit7_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit7_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit7_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit7_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit8_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit8_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit8_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit8_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit9_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit9_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit9_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit9_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit10_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit10_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit10_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit10_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit11_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit11_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit11_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit11_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit12_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit12_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit12_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit12_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit13_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit13_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit13_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit13_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit14_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit14_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit14_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit14_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit15_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit15_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit15_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit15_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit16_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit16_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit16_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit16_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit17_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit17_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit17_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit17_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit18_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit18_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit18_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit18_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit19_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit19_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit19_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit19_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit20_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit20_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit20_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit20_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit21_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit21_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit21_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit21_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit22_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit22_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit22_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit22_slice_11b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit23_slice_10a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit23_slice_10b (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit23_slice_11a (
l2t_ecc30b_dp_and_macro__ports_2__width_1 error_bit23_slice_11b (
//assign dout = din ^ error_bit ;
l2t_ecc30b_dp_xor_macro__stack_24r__width_24 dout_slice
//assign corrected_bit = {p16, p8, p4, p2, p1} ;
l2t_ecc30b_dp_buff_macro__stack_5r__width_5 buff_corrected_bit
.dout (corrected_bit[4:0]),
.din ({p16, p8, p4, p2, p1})
// xor macro for ports = 2,3
module l2t_ecc30b_dp_xor_macro__dxor_8x__ports_3__width_1 (
// xor macro for ports = 2,3
module l2t_ecc30b_dp_xor_macro__dxor_8x__ports_2__width_1 (
module l2t_ecc30b_dp_inv_macro__stack_1r__width_1 (
// and macro for ports = 2,3,4
module l2t_ecc30b_dp_and_macro__ports_2__width_1 (
// xor macro for ports = 2,3
module l2t_ecc30b_dp_xor_macro__stack_24r__width_24 (
module l2t_ecc30b_dp_buff_macro__stack_5r__width_5 (