design/sys/iop/libs.flist

-v $DV_ROOT/libs/cl/cl_rtl_ext.v
-v $DV_ROOT/libs/cl/cl_dp1/cl_dp1.v
-v $DV_ROOT/libs/cl/cl_u1/cl_u1.v
-v $DV_ROOT/libs/cl/cl_sc1/cl_sc1.v
-v $DV_ROOT/libs/cl/cl_a1/cl_a1.v
-v $DV_ROOT/libs/cl/cl_mc1/cl_mc1.v
-v $DV_ROOT/libs/rtl/n2_efuhdr1_ctl.v
-v $DV_ROOT/libs/tisram/soc/n2_l2d_sp_512kb_cust_l/n2_l2d_sp_512kb_cust/rtl/n2_l2d_sp_512kb_cust.v
-v $DV_ROOT/libs/tisram/soc/n2_efa_sp_256b_cust_l/n2_efa_sp_256b_cust/rtl/n2_efa_sp_256b_cust.v
-v $DV_ROOT/libs/tisram/soc/n2_l2t_sp_28kb_cust_l/n2_l2t_sp_28kb_cust/rtl/n2_l2t_sp_28kb_cust.v
-v $DV_ROOT/libs/tisram/core/n2_icd_sp_16p5kb_cust_l/n2_icd_sp_16p5kb_cust/rtl/n2_icd_sp_16p5kb_cust.v
-v $DV_ROOT/libs/tisram/core/n2_ict_sp_1920b_cust_l/n2_ict_sp_1920b_cust/rtl/n2_ict_sp_1920b_cust.v
-v $DV_ROOT/libs/tisram/core/n2_dca_sp_9kb_cust_l/n2_dca_sp_9kb_cust/rtl/n2_dca_sp_9kb_cust.v
-v $DV_ROOT/libs/tisram/core/n2_dta_sp_1920b_cust_l/n2_dta_sp_1920b_cust/rtl/n2_dta_sp_1920b_cust.v
-v $DV_ROOT/libs/n2sram/dp/n2_l2t_dp_16x160_cust_l/n2_l2t_dp_16x160_cust/rtl/n2_l2t_dp_16x160_cust.v
-v $DV_ROOT/libs/n2sram/dp/n2_l2t_dp_32x128_cust_l/n2_l2t_dp_32x128_cust/rtl/n2_l2t_dp_32x128_cust.v
-v $DV_ROOT/libs/n2sram/cams/n2_com_cm_32x40_cust_l/n2_com_cm_32x40_cust/rtl/n2_com_cm_32x40_cust.v
-v $DV_ROOT/libs/n2sram/cams/n2_com_cm_8x40_cust_l/n2_com_cm_8x40_cust/rtl/n2_com_cm_8x40_cust.v
-v $DV_ROOT/libs/n2sram/dp/n2_l2t_dp_32x160_cust_l/n2_l2t_dp_32x160_cust/rtl/n2_l2t_dp_32x160_cust.v
-v $DV_ROOT/libs/n2sram/async/n2_mcu_32x72async_dp_cust_l/n2_mcu_32x72async_dp_cust/rtl/n2_mcu_32x72async_dp_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_64x72_cust_l/n2_com_dp_64x72_cust/rtl/n2_com_dp_64x72_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x144s_cust_l/n2_com_dp_32x144s_cust/rtl/n2_com_dp_32x144s_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x144_cust_l/n2_com_dp_32x144_cust/rtl/n2_com_dp_32x144_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x32_cust_l/n2_com_dp_32x32_cust/rtl/n2_com_dp_32x32_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_128x16s_cust_l/n2_com_dp_128x16s_cust/rtl/n2_com_dp_128x16s_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x82_cust_l/n2_com_dp_32x82_cust/rtl/n2_com_dp_32x82_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_64x80_cust_l/n2_com_dp_64x80_cust/rtl/n2_com_dp_64x80_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_16x72_cust_l/n2_com_dp_16x72_cust/rtl/n2_com_dp_16x72_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x34_cust_l/n2_com_dp_32x34_cust/rtl/n2_com_dp_32x34_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_64x72s_cust_l/n2_com_dp_64x72s_cust/rtl/n2_com_dp_64x72s_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_16x32s_cust_l/n2_com_dp_16x32s_cust/rtl/n2_com_dp_16x32s_cust.v
-v $DV_ROOT/libs/n2sram/dp/n2_dva_dp_32x32_cust_l/n2_dva_dp_32x32_cust/rtl/n2_dva_dp_32x32_cust.v
-v $DV_ROOT/libs/n2sram/tlbs/n2_tlb_tl_64x59_cust_l/n2_tlb_tl_64x59_cust/rtl/n2_tlb_tl_64x59_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x72_cust_l/n2_com_dp_32x72_cust/rtl/n2_com_dp_32x72_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x152_cust_l/n2_com_dp_32x152_cust/rtl/n2_com_dp_32x152_cust.v
-v $DV_ROOT/libs/n2sram/cams/n2_stb_cm_64x45_cust_l/n2_stb_cm_64x45_cust/rtl/n2_stb_cm_64x45_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_64x84_cust_l/n2_com_dp_64x84_cust/rtl/n2_com_dp_64x84_cust.v
-v $DV_ROOT/libs/n2sram/tlbs/n2_tlb_tl_128x59_cust_l/n2_tlb_tl_128x59_cust/rtl/n2_tlb_tl_128x59_cust.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_32x84_cust_l/n2_com_dp_32x84_cust/rtl/n2_com_dp_32x84_cust.v
-v $DV_ROOT/libs/n2sram/cams/n2_com_cm_64x64_cust_l/n2_com_cm_64x64_cust/rtl/n2_com_cm_64x64_cust.v
-v $DV_ROOT/libs/n2sram/mp/n2_frf_mp_256x78_cust_l/n2_frf_mp_256x78_cust/rtl/n2_frf_mp_256x78_cust.v
-v $DV_ROOT/libs/n2sram/mp/n2_irf_mp_128x72_cust_l/n2_irf_mp_128x72_cust/rtl/n2_irf_mp_128x72_cust.v
-v $DV_ROOT/libs/n2sram/dp/n2_arf_dp_16x128_cust_l/n2_arf_dp_16x128_cust/rtl/n2_arf_dp_16x128_cust.v
-v $DV_ROOT/libs/n2sram/mp/n2_mam_mp_160x66_cust_l/n2_mam_mp_160x66_cust/rtl/n2_mam_mp_160x66_cust.v
-v $DV_ROOT/libs/clk/n2_clk_gl_cust_l/n2_clk_gl_cust/rtl/n2_clk_gl_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_ccx_cmp_cust/rtl/n2_clk_ccx_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_flop_bank_cust_l/n2_flop_bank_cust/rtl/n2_flop_bank_cust.v
-v $DV_ROOT/libs/clk/n2_clk_clstr_hdr1_cust_l/n2_clk_clstr_hdr1_cust/rtl/n2_clk_clstr_hdr1_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_db0_cmp_cust/rtl/n2_clk_db0_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_db0_io_cust/rtl/n2_clk_db0_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_db1_cmp_cust/rtl/n2_clk_db1_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_db1_io_cust/rtl/n2_clk_db1_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_efu_cmp_cust/rtl/n2_clk_efu_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_efu_io_cust/rtl/n2_clk_efu_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_l2b_cmp_cust/rtl/n2_clk_l2b_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_l2t_cmp_cust/rtl/n2_clk_l2t_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_mcu_cmp_cust/rtl/n2_clk_mcu_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_mcu_dr_cust/rtl/n2_clk_mcu_dr_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_mcu_io_cust/rtl/n2_clk_mcu_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_ncu_io_cust/rtl/n2_clk_ncu_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_ncu_cmp_cust/rtl/n2_clk_ncu_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_rst_cmp_cust/rtl/n2_clk_rst_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_rst_io_cust/rtl/n2_clk_rst_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_sii_cmp_cust/rtl/n2_clk_sii_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_sii_io_cust/rtl/n2_clk_sii_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_sio_cmp_cust/rtl/n2_clk_sio_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_sio_io_cust/rtl/n2_clk_sio_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_spc_cmp_cust/rtl/n2_clk_spc_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_clkchp_4sel_32x_cust_l/n2_clk_clkchp_4sel_32x_cust/rtl/n2_clk_clkchp_4sel_32x_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_tcu_cmp_cust/rtl/n2_clk_tcu_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_tcu_io_cust/rtl/n2_clk_tcu_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_mio_cmp_cust/rtl/n2_clk_mio_cmp_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_mio_io_cust/rtl/n2_clk_mio_io_cust.v
-v $DV_ROOT/design/sys/iop/mio/rtl/mio.v
-v $DV_ROOT/design/sys/iop/tcu/rtl/tcu_clkseq_ctl.v
-v $DV_ROOT/design/sys/iop/tcu/rtl/tcu_clkstp_ctl.v
-v $DV_ROOT/design/sys/iop/tcu/rtl/tcu_dbg_ctl.v
-v $DV_ROOT/design/sys/iop/tcu/rtl/tcu_dmo_ctl.v
-v $DV_ROOT/design/sys/iop/tcu/rtl/tcu_jtag_ctl.v
-v $DV_ROOT/design/sys/iop/tcu/rtl/tcu_jtag_tap_ctl.v
-v $DV_ROOT/design/sys/iop/tcu/rtl/tcu_mbist_ctl.v
-v $DV_ROOT/design/sys/iop/tcu/rtl/tcu_regs_ctl.v
-v $DV_ROOT/design/sys/iop/tcu/rtl/tcu_sigmux_ctl.v
-v $DV_ROOT/design/sys/iop/tcu/rtl/tcu_ucb_ctl.v
-v $DV_ROOT/design/sys/iop/tcu/rtl/tcu_ucbbusin8_ctl.v
-v $DV_ROOT/design/sys/iop/tcu/rtl/tcu_ucbbusout8_ctl.v
-v $DV_ROOT/design/sys/iop/spc/rtl/dmo_dp.v
-v $DV_ROOT/design/sys/iop/spc/rtl/spc_lb_ctl.v
-v $DV_ROOT/design/sys/iop/spc/rtl/spc_mb0_ctl.v
-v $DV_ROOT/design/sys/iop/spc/rtl/spc_mb1_ctl.v
-v $DV_ROOT/design/sys/iop/spc/rtl/spc_mb2_ctl.v
-v $DV_ROOT/design/sys/iop/spc/rtl/spc_msf0_dp.v
-v $DV_ROOT/design/sys/iop/spc/rtl/spc_msf1_dp.v
-v $DV_ROOT/design/sys/iop/spc/rtl/spc_rep1_dp.v
-v $DV_ROOT/design/sys/iop/spc/dec/rtl/dec_dcd_ctl.v
-v $DV_ROOT/design/sys/iop/spc/dec/rtl/dec_ded_ctl.v
-v $DV_ROOT/design/sys/iop/spc/dec/rtl/dec_del_ctl.v
-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu_ecc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu_ect_ctl.v
-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu_edp_dp.v
-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu_mdp_dp.v
-v $DV_ROOT/design/sys/iop/spc/exu/rtl/exu_rml_ctl.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fac_ctl.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fad_dp.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fdc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fdd_dp.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fec_ctl.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fgd_dp.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fic_ctl.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpe_dp.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpf_dp.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_fpy_dp.v
-v $DV_ROOT/design/sys/iop/spc/fgu/rtl/fgu_rep_dp.v
-v $DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_ipc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_ipd_dp.v
-v $DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_leg_ctl.v
-v $DV_ROOT/design/sys/iop/spc/gkt/rtl/gkt_pqm_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_cmt_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_csm_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_lsi_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_lsi_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_msb_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_cmu_msb_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_agc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_agd_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_asi_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_byp_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_cms_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_ctx_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_err_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_ftp_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_itc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_itd_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_red_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_tfc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ftu_tsm_ctl.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ibu_ibf_dp.v
-v $DV_ROOT/design/sys/iop/spc/ifu/rtl/ifu_ibu_ibq_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_adc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_arc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_ard_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_asc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_asd_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_cic_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_cid_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dac_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcd_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcp_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_dcs_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_lmc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_lmd_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_lru8_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_pic_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_pid_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_red_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_rep_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sbc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sbd_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sbs_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sec_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_sed_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_spd_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tgc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tgd_dp.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tlc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/lsu/rtl/lsu_tld_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_asd_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_ase_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_asi_ctl.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_eem_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_htc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_htd_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mbd_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mec_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mel_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_mem_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_sed_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_seg_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_sel_dp.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_tmc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_trc_ctl.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_trs_ctl.v
-v $DV_ROOT/design/sys/iop/spc/mmu/rtl/mmu_tsm_ctl.v
-v $DV_ROOT/design/sys/iop/spc/pku/rtl/pku_pck_ctl.v
-v $DV_ROOT/design/sys/iop/spc/pku/rtl/pku_pkd_dp.v
-v $DV_ROOT/design/sys/iop/spc/pku/rtl/pku_swl_ctl.v
-v $DV_ROOT/design/sys/iop/spc/pmu/rtl/pmu.v
-v $DV_ROOT/design/sys/iop/spc/pmu/rtl/pmu_pct_ctl.v
-v $DV_ROOT/design/sys/iop/spc/pmu/rtl/pmu_pdp_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_asi_ctl.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cel_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cep_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cer_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cth_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_cxi_ctl.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_dfd_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ecd_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ecg_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_eem_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_fls_ctl.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_mbd_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_npc_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_pct_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ras_ctl.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_ssd_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_sse_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tel_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tic_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_trl_ctl.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tsb_dp.v
-v $DV_ROOT/design/sys/iop/spc/tlu/rtl/tlu_tsd_dp.v
-v $DV_ROOT/design/sys/iop/rst/rtl/rst_cmp_ctl.v
-v $DV_ROOT/design/sys/iop/rst/rtl/rst_fsm_ctl.v
-v $DV_ROOT/design/sys/iop/rst/rtl/rst_io_ctl.v
-v $DV_ROOT/design/sys/iop/rst/rtl/rst_l1clkhdr_ctl_macro.v
-v $DV_ROOT/design/sys/iop/rst/rtl/rst_spare_ctl_macro__num_1.v
-v $DV_ROOT/design/sys/iop/rst/rtl/rst_spare_ctl_macro__num_4.v
-v $DV_ROOT/design/sys/iop/rst/rtl/rst_spare_ctl_macro__num_6.v
-v $DV_ROOT/design/sys/iop/rst/rtl/rst_ucbbusin4_ctl.v
-v $DV_ROOT/design/sys/iop/rst/rtl/rst_ucbbusout4_ctl.v
-v $DV_ROOT/design/sys/iop/rst/rtl/rst_ucbflow_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_c2ibuf32_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_c2ibuf4_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_c2ibufpio_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_c2ifc_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_c2ifcd_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_c2ifd_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_c2isc_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_c2iscd_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_c2isd_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_ctrl_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_eccchk11_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_eccchk16_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_eccchk6_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_eccgen11_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_eccgen6_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_fcd_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_i2cbuf32_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_i2cbuf32_ni_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_i2cbuf4_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_i2cbuf4_ni_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_i2cbufsii_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_i2cbuftcu_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_i2cfc_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_i2cfcd_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_i2cscd_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_i2csd_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_mb1_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_scd_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_ssiflow_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_ssisif_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_ssisrg8_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_ssitop_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_ssiui4_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_ssiuif_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_ssiuo4_ctl.v
-v $DV_ROOT/design/sys/iop/ncu/rtl/ncu_ucbbusin8_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_addrdp_dp.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_adrgen_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_adrq_dp.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_algnbf_dp.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_bnksm_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_bscan_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_crcn_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_crcnd_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_crcndf_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_crcs_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_crcsc_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_crcscf_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_crcsd_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_crcsdf_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_dmmdly_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_drif_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_drq_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_eccgen_dp.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_errq_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_fbd_dp.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_fbdic_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_fbdird_dp.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_fbdiwr_dp.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_fbdtm_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_fdoklu_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_fdout_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_frdbuf_dp.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_ibist_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_ibrx_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_ibtx_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_l2ecc_dp.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_l2if_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_l2rdmx_dp.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_latq_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_lndskw_dp.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_mbist_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_nibcor_dp.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_otq_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_pdmc_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_pdmchi_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_rdata_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_rdpctl_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_readdp_dp.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_reqq_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_ucb_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_ucbbuf_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_ucbin_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_ucbout_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_woq_ctl.v
-v $DV_ROOT/design/sys/iop/mcu/rtl/mcu_wrdp_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_arb_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_arbadr_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_arbdat_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_arbdec_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_csr_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_csreg_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_decc_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_deccck_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_dir_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_dirbuf_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_dirout_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_dirrep_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_dirtop_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_dirvec_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_dmo_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_dmorpt_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_ecc24b_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_ecc30b_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_ecc39_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_ecc39a_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_evctag_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_ffrpt_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_filbuf_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_iqu_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_ique_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_l2drpt_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_mb0_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_mb2_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_mbist_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_misbuf_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_mrep4x6_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_mrep8x16_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_mrep16x8_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_mrep2x64_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_mrep32x3_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_oqu_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_oque_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_pgen32b_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_rdmarpt_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_rdmat_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_rep_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_shdwscn_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_snp_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_snpd_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_tag_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_tagd_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_tagdp_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_taghdr_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_tagl_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_usaloc_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_vlddir_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_vuad_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_vuadcl_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_vuadio_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_vuadpm_dp.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_wbuf_ctl.v
-v $DV_ROOT/design/sys/iop/l2t/rtl/l2t_wbufrpt_dp.v
-v $DV_ROOT/design/sys/iop/l2b/rtl/l2b_ecc39_dp.v
-v $DV_ROOT/design/sys/iop/l2b/rtl/l2b_evict_dp.v
-v $DV_ROOT/design/sys/iop/l2b/rtl/l2b_fillbf_dp.v
-v $DV_ROOT/design/sys/iop/l2b/rtl/l2b_l2defu_ctl.v
-v $DV_ROOT/design/sys/iop/l2b/rtl/l2b_mb0_ctl.v
-v $DV_ROOT/design/sys/iop/l2b/rtl/l2b_rdmard_dp.v
-v $DV_ROOT/design/sys/iop/l2b/rtl/l2b_siu_dp.v
-v $DV_ROOT/design/sys/iop/efu/rtl/efu_fct_ctl.v
-v $DV_ROOT/design/sys/iop/efu/rtl/efu_l1clkhdr_ctl_macro.v
-v $DV_ROOT/design/sys/iop/efu/rtl/efu_l2t_ctl.v
-v $DV_ROOT/design/sys/iop/efu/rtl/efu_niu_ctl.v
-v $DV_ROOT/design/sys/iop/efu/rtl/efu_spare_ctl_macro__num_2.v
-v $DV_ROOT/design/sys/iop/efu/rtl/efu_spare_ctl_macro__num_4.v
-v $DV_ROOT/design/sys/iop/db1/rtl/db1_csr_ctl.v
-v $DV_ROOT/design/sys/iop/db1/rtl/db1_dbgprt_dp.v
-v $DV_ROOT/design/sys/iop/db1/rtl/db1_l1clkhdr_ctl_macro.v
-v $DV_ROOT/design/sys/iop/db1/rtl/db1_spare_ctl_macro__num_5.v
-v $DV_ROOT/design/sys/iop/db1/rtl/db1_spare_ctl_macro__num_6.v
-v $DV_ROOT/design/sys/iop/db1/rtl/db1_ucbbusin4_ctl.v
-v $DV_ROOT/design/sys/iop/db1/rtl/db1_ucbbusout4_ctl.v
-v $DV_ROOT/design/sys/iop/db1/rtl/db1_ucbflow_ctl.v
-v $DV_ROOT/design/sys/iop/db0/rtl/db0_l1clkhdr_ctl_macro.v
-v $DV_ROOT/design/sys/iop/db0/rtl/db0_red_dp.v
-v $DV_ROOT/design/sys/iop/db0/rtl/db0_reduct_ctl.v
-v $DV_ROOT/design/sys/iop/db0/rtl/db0_rtc_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_arb.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_arc_ctl.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_ard_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_l1clkhdr_ctl_macro.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_new_macro.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_rep.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_srq_ctl.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_trep.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/ccx_tstg.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_bfd_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_bfg_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpa.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsa.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsb.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsc.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsd.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpse.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsf.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_dpsg.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_mal_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_mar_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_mbl_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_mbr_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_mcl_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_mcr_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_ob1_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_ob2_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/cpx_rep_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/inv_diode_macro.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_bfd_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_bfg_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpa.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsa.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsb.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsc.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsd.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpse.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsf.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsg.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_dpsh.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_mal_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_mar_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_mbl_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_mbr_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_mcl_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_mcr_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_ob1_dp.v
-v $DV_ROOT/design/sys/iop/ccx/rtl/pcx_rep_dp.v
-v $DV_ROOT/design/sys/iop/fsr/rtl/fsr_lib.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcb.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_dcm_daemon.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/csr_sw.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcc.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_srq.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_srq_qdp.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_srq_qcp.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_srq_qci.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcs.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcs_ism.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcs_osm.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcs_sdp.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcd.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_frr_arbiter.v
-v $DV_ROOT/libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v
-v $DV_ROOT/libs/clk/n2_clk_clstr_hdr2_cust_l/n2_clk_clstr_hdr2_cust/rtl/n2_clk_clstr_hdr2_cust.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_dmu_io_cust/rtl/n2_clk_dmu_io_cust.v
-v $DV_ROOT/libs/clk/rtl/clkgen_dmu_io.v
-v $DV_ROOT/libs/n2sram/compiler/physical/n2_com_dp_16x132s_cust_l/n2_com_dp_16x132s_cust/rtl/n2_com_dp_16x132s_cust.v
-v $DV_ROOT/libs/n2sram/dp/n2_dmu_dp_144x149s_cust_l/n2_dmu_dp_144x149s_cust/rtl/n2_dmu_dp_144x149s_cust.v
-v $DV_ROOT/libs/n2sram/dp/n2_dmu_dp_128x132s_cust_l/n2_dmu_dp_128x132s_cust/rtl/n2_dmu_dp_128x132s_cust.v
-v $DV_ROOT/libs/n2sram/dp/n2_dmu_dp_512x60s_cust_l/n2_dmu_dp_512x60s_cust/rtl/n2_dmu_dp_512x60s_cust.v
-v $DV_ROOT/libs/n2sram/sp/n2_iom_sp_devtsb_cust_l/n2_iom_sp_devtsb_cust/rtl/n2_iom_sp_devtsb_cust.v
-v $DV_ROOT/libs/n2sram/cams/n2_mmu_cm_64x34s_cust_l/n2_mmu_cm_64x34s_cust/rtl/n2_mmu_cm_64x34s_cust.v
-v $DV_ROOT/libs/clk/rtl/clkgen_dmu_io.v
-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_dmu_io_cust/rtl/n2_clk_dmu_io_cust.v
-v $DV_ROOT/libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/dmu_common_simple_fifo.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/fire_dmc_common_srfifo.v
-v $DV_ROOT/design/sys/iop/pcie_common/rtl/dmu_common_scoreboard_controller.v
-v $DV_ROOT/verif/env/tcu/../../../libs/clk/n2_clk_pgrid_cust_l/n2_clk_ccu_io_cust/rtl/n2_clk_ccu_io_cust.v
-v $DV_ROOT/verif/env/tcu/../../../libs/clk/n2_clk_pgrid_cust_l/n2_clk_ccu_cmp_cust/rtl/n2_clk_ccu_cmp_cust.v
-v $DV_ROOT/verif/env/tcu/../../../libs/analog/n2_core_pll_cust_l/n2_core_pll_cust/rtl/n2_core_pll_cust.v
-v $DV_ROOT/verif/env/tcu/../../../libs/analog/n2_rng_cust_l/n2_rng_cust/rtl/n2_rng_cust.v
-v $DV_ROOT/verif/env/tcu/../../../design/sys/iop/ccu/rtl/ccu_io_rstgen.v
-v $DV_ROOT/verif/env/tcu/../../../design/sys/iop/ccu/rtl/ccu_divider.v
-v $DV_ROOT/verif/env/tcu/../../../design/sys/iop/ccu/rtl/ccu_pulse_shift.v
-v $DV_ROOT/verif/env/tcu/../../../design/sys/iop/ccu/rtl/ccu_hm_dr_reset_gen.v
-v $DV_ROOT/verif/env/tcu/../../../design/sys/iop/ccu/rtl/ccu_hm_pulse_shift.v
-v $DV_ROOT/verif/env/tcu/../../../design/sys/iop/ccu/rtl/ccu_hm_align_det.v
-v $DV_ROOT/verif/env/tcu/../../../design/sys/iop/ccu/rtl/ccu_hm_top.v
-v $DV_ROOT/verif/env/tcu/../../../design/sys/iop/ccu/rtl/ccu_cmp_dr_sync.v
-v $DV_ROOT/verif/env/tcu/../../../design/sys/iop/ccu/rtl/ccu_aux.v
-v $DV_ROOT/verif/env/tcu/../../../design/sys/iop/ccu/rtl/ccu_ucbflow_ctl.v
-v $DV_ROOT/verif/env/fc/fc_fast_bisi.v
-v $DV_ROOT/verif/env/fc/force_random_redundancy_bits.v
-v $DV_ROOT/verif/env/fc/../../../verif/model/verilog/mem/denali/denali_ddrII.v
-v $DV_ROOT/verif/env/fc/../../../verif/model/verilog/mem/denali/ddrII_soma.v
-v $DV_ROOT/verif/env/mcu/amb_dram_err_inject.v
-v $DV_ROOT/verif/env/mcu/ccu_pll_config.v
-v $DV_ROOT/verif/env/fc/../../../verif/env/tcu/tcu_mon.v
-v $DV_ROOT/verif/env/fc/../../../verif/env/tcu/ccu_mon.v
-v $DV_ROOT/verif/env/common/verilog/monitors/mcusat_cov_mon.v
-v $DV_ROOT/verif/env/common/verilog/monitors/n2_int.v
-v $DV_ROOT/verif/env/common/verilog/monitors/n2_int_latency.v
-v $DV_ROOT/verif/env/common/verilog/monitors/iommu_demap.v
-v $DV_ROOT/verif/env/common/verilog/misc/l2_scrub.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/fbdimm_clk_gen.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/amb_top.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/amb_init.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/ddr_io.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/crc.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/voting_logic.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/training_sequence_fsm.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/dtm_training.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/testing_state_fsm.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/send_ts0.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/sb_decode_crc.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/polling_state_fsm.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/nb_bit_lane_deskew.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/nb_encode_crc.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/nb_crc_error_injector.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/sb_crc_error_injector.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/idle_lfsr.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/alert_lfsr.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/config_state_fsm.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/channel_mon.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/fbdimm_nb_fsr.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/design/fbdimm_sb_fsr.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/library/delay.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/library/library.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/library/fifo/fifo.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/library/fifo/rptr_empty.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/library/fifo/sync_w2r.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/library/fifo/fifomem.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/library/fifo/sync_r2w.v
-v $DV_ROOT/verif/model/sun/../verilog/mem/fbdimm/library/fifo/wptr_full.v
-v $DV_ROOT/verif/env/common/verilog/err_random/L2_RST.v
-v $DV_ROOT/verif/env/common/verilog/err_random/l2err_ccm.v
-v $DV_ROOT/verif/env/common/verilog/err_random/l2ue_errinj.v
-v $DV_ROOT/verif/env/common/verilog/err_random/l2err_checker.v
-v $DV_ROOT/verif/env/common/verilog/err_random/l2cpx_checker.v
-v $DV_ROOT/verif/env/common/verilog/err_random/TagArray.v
-v $DV_ROOT/verif/env/common/verilog/err_random/vuaderr.v
+incdir+$DV_ROOT/verif/env/fc/+
+incdir+$DV_ROOT/verif/env/fc/../common/verilog/checkers+
+incdir+$DV_ROOT/verif/env/fc/../common/coverage+
+incdir+$DV_ROOT/verif/env/fc/../../../design/sys/iop/cpu/rtl+
+incdir+$DV_ROOT/verif/env/fc/../../../verif/env/tcu+
+incdir+$DV_ROOT/design/sys/iop/dmu/rtl
+incdir+$DV_ROOT/verif/env/fc/+
+incdir+$DV_ROOT/verif/env/fc/../common/verilog/checkers+
+incdir+$DV_ROOT/verif/env/fc/../common/coverage+
+incdir+$DV_ROOT/verif/env/fc/./vera/include
+incdir+$DV_ROOT/verif/env/mcu
+incdir+$DV_ROOT/verif/env/fc/../../../verif/env/tcu+
+incdir+$DV_ROOT/verif/env/common/verilog/monitors/+
+incdir+$DV_ROOT/verif/env/common/verilog/soc_sync/+
+incdir+$DV_ROOT/verif/env/common/verilog/err_random/+
+incdir+$DV_ROOT/verif/env/common/verilog/monitors/+
+incdir+$DV_ROOT/verif/env/common/verilog/reg_slam/+
+incdir+$DV_ROOT/verif/env/common/verilog/err_sync/+
+incdir+$DV_ROOT/verif/env/common/verilog/ldst_sync/+
+incdir+$DV_ROOT/verif/env/common/verilog/int_sync/+
+incdir+$DV_ROOT/verif/env/common/verilog/tlb_sync/+
+incdir+$DV_ROOT/verif/env/common/verilog/nas_car/+
+incdir+$DV_ROOT/verif/env/common/verilog/misc/+
+incdir+$DV_ROOT/verif/env/common/verilog/misc/../../vera/include+
+incdir+$DV_ROOT/verif/env/common/verilog/debug/+