design/sys/iop/ncu/rtl/ncu_i2cbuftcu_ctl.v

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: ncu_i2cbuftcu_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
//
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
//
// ========== Copyright Header End ============================================
`define RF_RDEN_OFFSTATE            1'b1

//====================================
`define NCU_INTMANRF_DEPTH         128
`define NCU_INTMANRF_DATAWIDTH      16
`define NCU_INTMANRF_ADDRWIDTH       7
//====================================

//====================================
`define NCU_MONDORF_DEPTH           64
`define NCU_MONDORF_DATAWIDTH       72
`define NCU_MONDORF_ADDRWIDTH        6
//====================================

//====================================
`define NCU_CPUBUFRF_DEPTH          32
`define NCU_CPUBUFRF_DATAWIDTH     144
`define NCU_CPUBUFRF_ADDRWIDTH       5
//====================================

//====================================
`define NCU_IOBUFRF_DEPTH          32
`define NCU_IOBUFRF_DATAWIDTH     144
`define NCU_IOBUFRF_ADDRWIDTH       5
//====================================

//====================================
`define NCU_IOBUF1RF_DEPTH          32
`define NCU_IOBUF1RF_DATAWIDTH      32
`define NCU_IOBUF1RF_ADDRWIDTH       5
//====================================

//====================================
`define NCU_INTBUFRF_DEPTH          32
`define NCU_INTBUFRF_DATAWIDTH     144
`define NCU_INTBUFRF_ADDRWIDTH       5
//====================================

//== fix me : need to remove when warm //
//== becomes available //
`define WMR_LENGTH              10'd999
`define WMR_LENGTH_P1           10'd1000

//// NCU CSR_MAN address   80_0000_xxxx ////
`define NCU_CSR_MAN                     16'h0000
`define NCU_CREG_INTMAN                 16'h0000
//`define NCU_CREG_INTVECDISP           16'h0800
`define NCU_CREG_MONDOINVEC             16'h0a00
`define NCU_CREG_SERNUM                 16'h1000
`define NCU_CREG_FUSESTAT               16'h1008
`define NCU_CREG_COREAVAIL              16'h1010
`define NCU_CREG_BANKAVAIL              16'h1018
`define NCU_CREG_BANK_ENABLE            16'h1020
`define NCU_CREG_BANK_ENABLE_STATUS     16'h1028
`define NCU_CREG_L2_HASH_ENABLE         16'h1030
`define NCU_CREG_L2_HASH_ENABLE_STATUS  16'h1038


`define NCU_CREG_MEM32_BASE     16'h2000
`define NCU_CREG_MEM32_MASK     16'h2008
`define NCU_CREG_MEM64_BASE     16'h2010
`define NCU_CREG_MEM64_MASK     16'h2018
`define NCU_CREG_IOCON_BASE     16'h2020
`define NCU_CREG_IOCON_MASK     16'h2028
`define NCU_CREG_MMUFSH         16'h2030

`define NCU_CREG_ESR            16'h3000
`define NCU_CREG_ELE            16'h3008
`define NCU_CREG_EIE            16'h3010
`define NCU_CREG_EJR            16'h3018
`define NCU_CREG_FEE            16'h3020
`define NCU_CREG_PER            16'h3028
`define NCU_CREG_SIISYN         16'h3030
`define NCU_CREG_NCUSYN         16'h3038
`define NCU_CREG_SCKSEL         16'h3040
`define NCU_CREG_DBGTRIG_EN     16'h4000

//// NUC CSR_MONDO address 80_0004_xxxx ////
`define NCU_CSR_MONDO           16'h0004
`define NCU_CREG_MDATA0         16'h0000
`define NCU_CREG_MDATA1         16'h0200
`define NCU_CREG_MDATA0_ALIAS   16'h0400
`define NCU_CREG_MDATA1_ALIAS   16'h0600
`define NCU_CREG_MBUSY          16'h0800
`define NCU_CREG_MBUSY_ALIAS    16'h0a00


// ASI shared reg 90_xxxx_xxxx//
`define NCU_ASI_A_HIT                   10'h104 // 6-bits cpuid and thread id are "x"
`define NCU_ASI_B_HIT                   10'h1CC // 6-bits cpuid and thread id are "x"
`define NCU_ASI_C_HIT                   10'h114 // 6-bits cpuid and thread id are "x"
`define NCU_ASI_COREAVAIL               16'h0000
`define NCU_ASI_CORE_ENABLE_STATUS      16'h0010
`define NCU_ASI_CORE_ENABLE             16'h0020
`define NCU_ASI_XIR_STEERING            16'h0030
`define NCU_ASI_CORE_RUNNINGRW          16'h0050
`define NCU_ASI_CORE_RUNNING_STATUS     16'h0058
`define NCU_ASI_CORE_RUNNING_W1S        16'h0060
`define NCU_ASI_CORE_RUNNING_W1C        16'h0068
`define NCU_ASI_INTVECDISP              16'h0000
`define NCU_ASI_ERR_STR                 16'h1000
`define NCU_ASI_WMR_VEC_MASK            16'h0018
`define NCU_ASI_CMP_TICK_ENABLE         16'h0038


//// UCB packet type ////
`define UCB_READ_NACK   4'b0000    // ack/nack types
`define UCB_READ_ACK    4'b0001
`define UCB_WRITE_ACK   4'b0010
`define UCB_IFILL_ACK   4'b0011
`define UCB_IFILL_NACK  4'b0111

`define UCB_READ_REQ    4'b0100    // req types
`define UCB_WRITE_REQ   4'b0101
`define UCB_IFILL_REQ   4'b0110

`define UCB_INT         4'b1000    // plain interrupt
`define UCB_INT_VEC     4'b1100    // interrupt with vector
`define UCB_INT_SOC_UE  4'b1001    // soc interrup ue
`define UCB_INT_SOC_CE  4'b1010    // soc interrup ce
`define UCB_RESET_VEC   4'b0101    // reset with vector
`define UCB_IDLE_VEC    4'b1110    // idle with vector
`define UCB_RESUME_VEC  4'b1111    // resume with vector

`define UCB_INT_SOC     4'b1101    // soc interrup ce


//// PCX packet type ////
`define PCX_LOAD_RQ     5'b00000
`define PCX_IMISS_RQ    5'b10000
`define PCX_STORE_RQ    5'b00001
`define PCX_FWD_RQs     5'b01101
`define PCX_FWD_RPYs    5'b01110

//// CPX packet type ////
//`define CPX_LOAD_RET  4'b0000
`define CPX_LOAD_RET    4'b1000
`define CPX_ST_ACK      4'b0100
//`define CPX_IFILL_RET 4'b0001
`define CPX_IFILL_RET   4'b1001
`define CPX_INT_RET     4'b0111
`define CPX_INT_SOC     4'b1101
//`define CPX_FWD_RQ_RET        4'b1010
//`define CPX_FWD_RPY_RET       4'b1011


//// Global CSR decode ////
`define NCU_CSR         8'h80
`define NIU_CSR         8'h81
//`define RNG_CSR               8'h82
`define DBG1_CSR               8'h86
`define CCU_CSR         8'h83
`define MCU_CSR         8'h84
`define TCU_CSR         8'h85
`define DMU_CSR         8'h88
`define RCU_CSR         8'h89
`define NCU_ASI         8'h90
                        /////8'h91 ~ 9F reserved
                        /////8'hA0 ~ BF L2 CSR////
`define DMU_PIO         4'hC   // C0 ~ CF
                        /////8'hB0 ~ FE reserved
`define SSI_CSR         8'hFF


//// NCU_SSI ////
`define SSI_ADDR                12'hFF_F
`define SSI_ADDR_TIMEOUT_REG    40'hFF_0001_0088
`define SSI_ADDR_LOG_REG        40'hFF_0000_0018

`define IF_IDLE 2'b00
`define IF_ACPT 2'b01
`define IF_DROP 2'b10

`define SSI_IDLE     3'b000
`define SSI_REQ      3'b001
`define SSI_WDATA    3'b011
`define SSI_REQ_PAR  3'b101
`define SSI_ACK      3'b111
`define SSI_RDATA    3'b110
`define SSI_ACK_PAR  3'b010


module ncu_i2cbuftcu_ctl (
  iol2clk,
  scan_in,
  scan_out,
  tcu_pce_ov,
  tcu_clk_stop,
  tcu_scan_en,
  tcu_aclk,
  tcu_bclk,
  vld,
  data,
  stall,
  tap_iob_busy,
  iob_tap_packet,
  iob_tap_packet_vld) ;
wire buf_obj_ff_scanin;
wire buf_obj_ff_scanout;
wire [127:0] buf_obj;
wire l1clk;
wire buf_obj_vld_ff_scanin;
wire buf_obj_vld_ff_scanout;
wire buf_obj_vld;
wire buf_obj_vld_next;
wire outdata_buf_busy;
wire [15:0] outdata_vec_in;
wire [15:0] outdata_vec;
wire [127:0] outdata_buf;
wire rdy0_ff_scanin;
wire rdy0_ff_scanout;
wire rdy0;
wire rdy1_ff_scanin;
wire rdy1_ff_scanout;
wire rdy1;
wire stall_d1_ff_scanin;
wire stall_d1_ff_scanout;
wire stall_d1;
wire load_outdata;
wire shift_outdata;
wire [15:0] outdata_vec_next;
wire outdata_vec_ff_scanin;
wire outdata_vec_ff_scanout;
wire [127:0] outdata_buf_next;
wire outdata_buf_ff_scanin;
wire outdata_buf_ff_scanout;
wire siclk;
wire soclk;
wire se;
wire pce_ov;
wire stop;


// Globals
input           iol2clk;
input           scan_in;
output          scan_out;
input           tcu_pce_ov;
input           tcu_clk_stop;
input           tcu_scan_en;
input           tcu_aclk;
input           tcu_bclk;

// UCB bus interface
output          vld;
output [7 :0]   data;
input           stall;

// Local interface
output          tap_iob_busy;
input [127:0]   iob_tap_packet;
input           iob_tap_packet_vld;

// Local signals


ncu_i2cbuftcu_ctl_msff_ctl_macro__en_1__width_128 buf_obj_ff
                                (
                                .scan_in(buf_obj_ff_scanin),
                                .scan_out(buf_obj_ff_scanout),
                                .dout           (buf_obj[127:0] ),
                                .l1clk          (l1clk),
                                .en             (iob_tap_packet_vld),
                                .din            (iob_tap_packet[127:0]),
  .siclk(siclk),
  .soclk(soclk)
                                );

ncu_i2cbuftcu_ctl_msff_ctl_macro__width_1 buf_obj_vld_ff
                                (
                                .scan_in(buf_obj_vld_ff_scanin),
                                .scan_out(buf_obj_vld_ff_scanout),
                                .dout           (buf_obj_vld),
                                .l1clk          (l1clk),
                                .din            (buf_obj_vld_next),
  .siclk(siclk),
  .soclk(soclk)
                                );


assign buf_obj_vld_next = buf_obj_vld ? outdata_buf_busy : iob_tap_packet_vld ;
assign tap_iob_busy = buf_obj_vld;

assign outdata_vec_in[15:0] = (buf_obj[3:0]==`UCB_READ_NACK) ? 16'h00ff : 16'hffff ;

////////////////////////////////////////////////////////////////////////
// Code starts here
////////////////////////////////////////////////////////////////////////
/************************************************************
 * UCB bus interface flops
 ************************************************************/
assign   vld = outdata_vec[0];
assign   data[7 :0] = outdata_buf[7 :0];


ncu_i2cbuftcu_ctl_msff_ctl_macro__width_1 rdy0_ff
                                (
                                .scan_in(rdy0_ff_scanin),
                                .scan_out(rdy0_ff_scanout),
                                .dout           (rdy0),
                                .l1clk          (l1clk),
                                .din            (1'b1),
  .siclk(siclk),
  .soclk(soclk)
                                );

ncu_i2cbuftcu_ctl_msff_ctl_macro__width_1 rdy1_ff
                                (
                                .scan_in(rdy1_ff_scanin),
                                .scan_out(rdy1_ff_scanout),
                                .dout           (rdy1),
                                .l1clk          (l1clk),
                                .din            (rdy0),
  .siclk(siclk),
  .soclk(soclk)
                                );


ncu_i2cbuftcu_ctl_msff_ctl_macro__en_1__width_1 stall_d1_ff
                                (
                                .scan_in(stall_d1_ff_scanin),
                                .scan_out(stall_d1_ff_scanout),
                                .dout           (stall_d1),
                                .l1clk          (l1clk),
                                .en             (rdy1),
                                .din            (stall),
  .siclk(siclk),
  .soclk(soclk)
                                );

/************************************************************
 * Outbound Data
 ************************************************************/
// accept new data only if there is none being processed
//assign  load_outdata = outdata_buf_wr & ~outdata_buf_busy;
assign  load_outdata = buf_obj_vld & ~outdata_buf_busy;

assign  outdata_buf_busy = outdata_vec[0] | stall_d1;

assign  shift_outdata = outdata_vec[0] & ~stall_d1;

assign  outdata_vec_next[15 :0] = load_outdata  ? outdata_vec_in[15 :0] :
                                shift_outdata ? {1'b0,outdata_vec[15 :1]} :
                                                outdata_vec[15 :0] ;

ncu_i2cbuftcu_ctl_msff_ctl_macro__width_16 outdata_vec_ff
                                (
                                .scan_in(outdata_vec_ff_scanin),
                                .scan_out(outdata_vec_ff_scanout),
                                .dout           (outdata_vec[15 :0]),
                                .l1clk          (l1clk),
                                .din            (outdata_vec_next[15 :0]),
  .siclk(siclk),
  .soclk(soclk)
                                );

assign  outdata_buf_next[127:0] = load_outdata  ? buf_obj[127:0] :
                                  shift_outdata ? (outdata_buf[127:0] >> 8 ) :
                                                   outdata_buf[127:0] ;

ncu_i2cbuftcu_ctl_msff_ctl_macro__width_128 outdata_buf_ff
                                (
                                .scan_in(outdata_buf_ff_scanin),
                                .scan_out(outdata_buf_ff_scanout),
                                .dout           (outdata_buf[127:0]),
                                .l1clk          (l1clk),
                                .din            (outdata_buf_next[127:0]),
  .siclk(siclk),
  .soclk(soclk)
                                );


/**** adding clock header ****/
ncu_i2cbuftcu_ctl_l1clkhdr_ctl_macro clkgen (
                                .l2clk  (iol2clk),
                                .l1en   (1'b1),
                                .l1clk  (l1clk),
  .pce_ov(pce_ov),
  .stop(stop),
  .se(se)
                                );

/*** building tcu port ***/
assign  siclk = tcu_aclk;
assign  soclk = tcu_bclk;
assign     se = tcu_scan_en;
assign  pce_ov = tcu_pce_ov;
assign  stop = tcu_clk_stop;

// fixscan start:
assign buf_obj_ff_scanin         = scan_in                  ;
assign buf_obj_vld_ff_scanin     = buf_obj_ff_scanout       ;
assign rdy0_ff_scanin            = buf_obj_vld_ff_scanout   ;
assign rdy1_ff_scanin            = rdy0_ff_scanout          ;
assign stall_d1_ff_scanin        = rdy1_ff_scanout          ;
assign outdata_vec_ff_scanin     = stall_d1_ff_scanout      ;
assign outdata_buf_ff_scanin     = outdata_vec_ff_scanout   ;
assign scan_out                  = outdata_buf_ff_scanout   ;
// fixscan end:
endmodule // ncu_i2cbuftcu_ctl


// any PARAMS parms go into naming of macro

module ncu_i2cbuftcu_ctl_msff_ctl_macro__en_1__width_128 (
  din,
  en,
  l1clk,
  scan_in,
  siclk,
  soclk,
  dout,
  scan_out);
wire [127:0] fdin;
wire [126:0] so;

  input [127:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [127:0] dout;
  output scan_out;
assign fdin[127:0] = (din[127:0] & {128{en}}) | (dout[127:0] & ~{128{en}});


dff #(128)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[127:0]),
.si({scan_in,so[126:0]}),
.so({so[126:0],scan_out}),
.q(dout[127:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ncu_i2cbuftcu_ctl_msff_ctl_macro__width_1 (
  din,
  l1clk,
  scan_in,
  siclk,
  soclk,
  dout,
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = din[0:0];


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ncu_i2cbuftcu_ctl_msff_ctl_macro__en_1__width_1 (
  din,
  en,
  l1clk,
  scan_in,
  siclk,
  soclk,
  dout,
  scan_out);
wire [0:0] fdin;

  input [0:0] din;
  input en;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [0:0] dout;
  output scan_out;
assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}});


dff #(1)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[0:0]),
.si(scan_in),
.so(scan_out),
.q(dout[0:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ncu_i2cbuftcu_ctl_msff_ctl_macro__width_16 (
  din,
  l1clk,
  scan_in,
  siclk,
  soclk,
  dout,
  scan_out);
wire [15:0] fdin;
wire [14:0] so;

  input [15:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [15:0] dout;
  output scan_out;
assign fdin[15:0] = din[15:0];


dff #(16)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[15:0]),
.si({scan_in,so[14:0]}),
.so({so[14:0],scan_out}),
.q(dout[15:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ncu_i2cbuftcu_ctl_msff_ctl_macro__width_128 (
  din,
  l1clk,
  scan_in,
  siclk,
  soclk,
  dout,
  scan_out);
wire [127:0] fdin;
wire [126:0] so;

  input [127:0] din;
  input l1clk;
  input scan_in;


  input siclk;
  input soclk;

  output [127:0] dout;
  output scan_out;
assign fdin[127:0] = din[127:0];


dff #(128)  d0_0 (
.l1clk(l1clk),
.siclk(siclk),
.soclk(soclk),
.d(fdin[127:0]),
.si({scan_in,so[126:0]}),
.so({so[126:0],scan_out}),
.q(dout[127:0])
);


endmodule


// any PARAMS parms go into naming of macro

module ncu_i2cbuftcu_ctl_l1clkhdr_ctl_macro (
  l2clk,
  l1en,
  pce_ov,
  stop,
  se,
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_sc1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule