design/sys/iop/niu/rtl/fflp_flow_fifo.v

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// OpenSPARC T2 Processor File: fflp_flow_fifo.v
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/*project name:  NIU                                                  */
/*module name:   fflp_flow_fifo                                       */
/*description:   contains the data storage for cam search results to  */
/*               hash table lookup and final merge function.          */
/*                                                                    */
/*parent module in:                                                   */
/*child modules in:  none                                             */
/*interface modules:                                                  */
/*author name:       Jeanne Cai                                       */
/*date created:      03-17-04                                         */
/*                                                                    */
/*              Copyright (c) 2004, Sun Microsystems, Inc.            */
/*                   Sun Proprietary and Confidential                 */
/*                                                                    */
/*modifications:                                                      */
/*                                                                    */
module fflp_flow_fifo
                (
                clk,
                reset,
                dout,
                hdr_fifo_empty,
                hdr_fifo_full,
                din,
                wen,
                ren
                );

parameter dwidth = 16;

input                   clk;
input                   reset;
input   [dwidth-1:0]    din;
input                   wen; //increments wptr and writes in din
input                   ren; //increments rptr

output  [dwidth-1:0]    dout;
output                  hdr_fifo_empty;
output                  hdr_fifo_full;


wire[dwidth-1:0]        dout;

`ifdef NEPTUNE
reg[dwidth-1:0]         data_mem[0:3];
reg[2:0]                wptr;
reg[2:0]                rptr;

wire[1:0]               wptr1           = wptr[1:0];
wire[1:0]               rptr1           = rptr[1:0];

wire                    hdr_fifo_full   = (wptr[2] != rptr[2]) & (wptr1 == rptr1);
wire                    hdr_fifo_empty  = (wptr[2] == rptr[2]) & (wptr1 == rptr1);

`else
reg[dwidth-1:0]         data_mem[0:1];
reg[1:0]                wptr;
reg[1:0]                rptr;

wire                    wptr1           = wptr[0];
wire                    rptr1           = rptr[0];

wire                    hdr_fifo_full   = (wptr[1] != rptr[1]) & (wptr1 == rptr1);
wire                    hdr_fifo_empty  = (wptr[1] == rptr[1]) & (wptr1 == rptr1);

`endif


always @(posedge clk)
if (wen)
        data_mem[wptr1] <= din;

assign dout     = data_mem[rptr1];

always @(posedge clk)
if (reset)
        wptr <= 0;
else if (wen)
        wptr <=  wptr + 1;
else
        wptr <=  wptr;

always @(posedge clk)
if (reset)
        rptr <= 0;
else if (ren)
        rptr <=  rptr + 1;
else
        rptr <=  rptr;


endmodule