Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / niu / rtl / niu_pio_virt_decode.v
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// OpenSPARC T2 Processor File: niu_pio_virt_decode.v
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/*%W% %G%*/
/*****************************************************************
*
* File Name : niu_pio_virt_decode.v
* Author Name : Maya Suresh
* Description : Virtualization Decoder
*
* Parent Module: niu_pio_regs.v
* Child Module:
* Interface Mod:
* Date Created : 04/25/05
*
* Copyright (c) 2020, Sun Microsystems, Inc.
* Sun Proprietary and Confidential
*
* Modification :
*
****************************************************************/
module niu_pio_virt_decode (
// Outputs
virt_addr, pio_virt_sel_ok, fflp_virt_sel_ok,
dma_virt_sel_ok,
// Inputs
addr, fc0_v, fc1_v, fc2_v, fc3_v
);
output [26:0] virt_addr ;
output pio_virt_sel_ok ;
output fflp_virt_sel_ok ;
output dma_virt_sel_ok;
input [26:0] addr ;
input fc0_v ;
input fc1_v ;
input fc2_v ;
input fc3_v ;
reg [26:0] virt_addr ;
reg pio_virt_sel_ok ;
reg fflp_virt_sel_ok ;
reg dma_virt_sel_ok;
always @ (addr or
fc0_v or
fc1_v or
fc2_v or
fc3_v )
begin
virt_addr[26:0] = 27'b0;
pio_virt_sel_ok = 1'b0 ;
fflp_virt_sel_ok = 1'b0 ;
dma_virt_sel_ok = 1'b0 ;
// Function Zero Virtualization
if (fc0_v) // Function Zero Virtualization Decode
begin
// Code for DMA Virtualization
if (addr[23:13] == 11'b0000_0000_000)
begin
virt_addr[26:0] = addr[26:0];
dma_virt_sel_ok = 1'b1 ;
end
if (addr[23:13] == 11'b0000_0000_010)
begin
virt_addr[26:0] = addr[26:0];
dma_virt_sel_ok = 1'b1 ;
end
// END
if (addr[15:8] == 8'b0010_0000)
begin
virt_addr[23:0] = {8'b1000_0000,addr[7:5],8'b0,addr[4:0]};
virt_addr[26:24]= addr[26:24];
pio_virt_sel_ok = 1'b1 ;
end
if (addr[15:8] == 8'b0110_0000)
begin
virt_addr[23:0] = {8'b1000_0001,addr[7:5],8'b0,addr[4:0]};
virt_addr[26:24]= addr[26:24];
pio_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0010_0001_0000_0000)
begin
virt_addr[23:0] = {4'b0011,20'b0};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0010_0001_0000_1000)
begin
virt_addr[23:0] = {4'b0011,16'b0,4'b1000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0010_0001_0001_0000)
begin
virt_addr[23:0] = {4'b0011,12'b0,4'b0001,4'b0000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0110_0001_0000_0000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b0010,12'b0};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0110_0001_0000_1000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b0010,8'b0,4'b1000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0110_0001_0001_0000)
begin
fflp_virt_sel_ok = 1'b1 ;
virt_addr[23:0] = {4'b0011,4'b0000,4'b0010,4'b0000,4'b0001,4'b0000};
virt_addr[26:24]= addr[26:24];
end
end
// Function One Virtualization
if (fc1_v) // Function Zero Virtualization Decode
begin
// Code for DMA Virtualization
if (addr[23:13] == 11'b0000_0000_000)
begin
virt_addr[26:0] = addr[26:0];
dma_virt_sel_ok = 1'b1 ;
end
if (addr[23:13] == 11'b0000_0000_010)
begin
virt_addr[26:0] = addr[26:0];
dma_virt_sel_ok = 1'b1 ;
end
// END
if (addr[15:8] == 8'b0010_0000)
begin
virt_addr[23:0] = {8'b1000_0010,addr[7:5],8'b0,addr[4:0]};
virt_addr[26:24]= addr[26:24];
pio_virt_sel_ok = 1'b1 ;
end
if (addr[15:8] == 8'b0110_0000)
begin
virt_addr[23:0] = {8'b1000_0011,addr[7:5],8'b0,addr[4:0]};
virt_addr[26:24]= addr[26:24];
pio_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0010_0001_0000_0000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b0100,8'b0,4'b0000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0010_0001_0000_1000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b0100,8'b0,4'b1000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0010_0001_0001_0000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b0100,4'b0,4'b0001,4'b0000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0110_0001_0000_0000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b0110,8'b0,4'b0000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0110_0001_0000_1000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b0110,8'b0,4'b1000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0110_0001_0001_0000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b0110,4'b0,4'b0001,4'b0000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
end
// Function Two Virtualization
if (fc2_v) // Function Zero Virtualization Decode
begin
// Code for DMA Virtualization
if (addr[23:13] == 11'b0000_0000_000)
begin
virt_addr[26:0] = addr[26:0];
dma_virt_sel_ok = 1'b1 ;
end
if (addr[23:13] == 11'b0000_0000_010)
begin
virt_addr[26:0] = addr[26:0];
dma_virt_sel_ok = 1'b1 ;
end
// END
if (addr[15:8] == 8'b0010_0000)
begin
virt_addr[23:0] = {8'b1000_0100,addr[7:5],8'b0,addr[4:0]};
virt_addr[26:24]= addr[26:24];
pio_virt_sel_ok = 1'b1 ;
end
if (addr[15:8] == 8'b0110_0000)
begin
virt_addr[23:0] = {8'b1000_0101,addr[7:5],8'b0,addr[4:0]};
virt_addr[26:24]= addr[26:24];
pio_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0010_0001_0000_0000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b1000,8'b0,4'b0000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0010_0001_0000_1000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b1000,8'b0,4'b1000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0010_0001_0001_0000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b1000,4'b0,4'b0001,4'b0000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0110_0001_0000_0000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b1010,8'b0,4'b0000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0110_0001_0000_1000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b1010,8'b0,4'b1000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0110_0001_0001_0000)
begin
fflp_virt_sel_ok = 1'b1 ;
virt_addr[26:24]= addr[26:24];
virt_addr[23:0] = {4'b0011,4'b0000,4'b1010,4'b0,4'b0001,4'b0000};
end
end
// Function Three Virtualization
if (fc3_v) // Function Zero Virtualization Decode
begin
// Code for DMA Virtualization
if (addr[23:13] == 11'b0000_0000_000)
begin
virt_addr[26:0] = addr[26:0];
dma_virt_sel_ok = 1'b1 ;
end
if (addr[23:13] == 11'b0000_0000_010)
begin
virt_addr[26:0] = addr[26:0];
dma_virt_sel_ok = 1'b1 ;
end
// END
if (addr[15:8] == 8'b0010_0000)
begin
virt_addr[23:0] = {8'b1000_0110,addr[7:5],8'b0,addr[4:0]};
virt_addr[26:24]= addr[26:24];
pio_virt_sel_ok = 1'b1 ;
end
if (addr[15:8] == 8'b0110_0000)
begin
virt_addr[23:0] = {8'b1000_0111,addr[7:5],8'b0,addr[4:0]};
virt_addr[26:24]= addr[26:24];
pio_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0010_0001_0000_0000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b1100,8'b0,4'b0000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0010_0001_0000_1000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b1100,8'b0,4'b1000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0010_0001_0001_0000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b1100,4'b0,4'b0001,4'b0000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0110_0001_0000_0000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b1110,8'b0,4'b0000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0110_0001_0000_1000)
begin
virt_addr[23:0] = {4'b0011,4'b0000,4'b1110,8'b0,4'b1000};
virt_addr[26:24]= addr[26:24];
fflp_virt_sel_ok = 1'b1 ;
end
if (addr[15:0] == 16'b0110_0001_0001_0000)
begin
fflp_virt_sel_ok = 1'b1 ;
virt_addr[26:24]= addr[26:24];
virt_addr[23:0] = {4'b0011,4'b0000,4'b1110,4'b0,4'b0001,4'b0000};
end
end
end
endmodule // niu_pio_virt_decode