design/sys/iop/niu/rtl/niu_ram_1024x146.v

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//
// OpenSPARC T2 Processor File: niu_ram_1024x146.v
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/**********************************************************
***********************************************************

    Project         : Niu

    File name       : niu_ram_1024x146.v

    Module(s) name  : niu_ram_1024x146

    Parent modules  :

    Child modules   :

    Author's name   : George Chu

    Date            : April. 2004

    Description     :

    Synthesis Notes:

    Modification History:
    Date       Description
    ----       -----------

************************************************************
***********************************************************/

`timescale 1ns/10ps

module niu_ram_1024x146 (
                         tcu_scan_en,
                         tcu_aclk,
                         tcu_bclk,
                         tcu_se_scancollar_in,
                         tcu_se_scancollar_out,
                         tcu_clk_stop,
                         tcu_pce_ov,
                         tcu_array_wr_inhibit,
                         tcu_array_bypass,
                         scan_in,
                         scan_out,

                         data_inp,
                         addr_rd,
                         addr_wt,
                         wt_enable,
                         cs_rd,
                         clk,
                         data_out
                       );

input           tcu_scan_en;
input           tcu_aclk;
input           tcu_bclk;
input           tcu_se_scancollar_in;
input           tcu_se_scancollar_out;
input           tcu_clk_stop;
input           tcu_pce_ov;
input           tcu_array_wr_inhibit;
input           tcu_array_bypass;
input           scan_in;
output          scan_out;

input   [145:0] data_inp;      // data_input,               via port_B
input     [9:0] addr_rd;       //  read_address,            via port_A
input     [9:0] addr_wt;       // write_address,            via port_B
input           wt_enable;     // write_enable,             via port_B
input           cs_rd;         // chip_selet_rd_port,     i.e., port_A
input           clk;           // clock
output  [145:0] data_out;      // data read out, via port_A

wire    [145:0] data_out;
wire            scan_out;

  n2_niu_dp_1024x146s_cust ram_1024x146_0 (
                                           .tcu_scan_en           (tcu_scan_en),
                                           .tcu_aclk              (tcu_aclk),
                                           .tcu_bclk              (tcu_bclk),
                                           .tcu_se_scancollar_in  (tcu_se_scancollar_in),
                                           .tcu_se_scancollar_out (tcu_se_scancollar_out),
                                           .tcu_clk_stop          (tcu_clk_stop),
                                           .tcu_pce_ov            (tcu_pce_ov),
                                           .tcu_array_wr_inhibit  (tcu_array_wr_inhibit),
                                           .tcu_array_bypass      (tcu_array_bypass),
                                           .scan_in               (scan_in),
                                           .scan_out              (scan_out),
                                           .wr_adr                (addr_wt[9:0]),
                                           .wr_en                 (wt_enable),
                                           .rd_adr                (addr_rd[9:0]),
                                           .rd_en                 (cs_rd),
                                           .din                   (data_inp[145:0]),
                                           .dout                  (data_out[145:0]),
                                           .rdclk                 (clk),
                                           .wrclk                 (clk)
                                          );

endmodule