design/sys/iop/niu/rtl/niu_regin_sram_model.v

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// OpenSPARC T2 Processor File: niu_regin_sram_model.v
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/*************************************************************************
 *
 * File Name    : niu_regin_sram_model
 * Author Name  : John Lo
 * Description  : A parameterizable register in SRAM model.
 * Parent Module:
 * Child  Module:
 * Interface Mod:
 * Date Created : 4/15/2004
 *
 * Copyright (c) 2020, Sun Microsystems, Inc.
 * Sun Proprietary and Confidential
 *
 * Modification :
 *
 * Synthesis Notes:
 *
 *************************************************************************/

module niu_regin_sram_model (
din,
we,
waddr,
clk,
re,
raddr,
dout
);

parameter WIDTH = 16,           // Width (# of bits)
          ADDR_BITS = 4,        // number of address bits
          DEPTH = 1<<ADDR_BITS; // number of entries

//======================================================================
// Input/Outputs declarations
//======================================================================

input   [WIDTH-1:0]     din;    // data in
input                   we;     // Write strobe
input   [ADDR_BITS-1:0] waddr;  // write address
input                   clk;    // Clock
input                   re;     // read enable
input   [ADDR_BITS-1:0] raddr;  // read address
output  [WIDTH-1:0]     dout;

wire    [WIDTH-1:0]     dout;

// The memory array
reg     [WIDTH-1:0]     mem [DEPTH-1:0];
reg     [ADDR_BITS-1:0] raddr_reg;  // read address
wire    [ADDR_BITS-1:0] raddr;      // read address

// latch read address
always @(posedge clk)
  if (re)
     raddr_reg <= raddr;
  else
     raddr_reg <= raddr_reg;

// Output mux
assign    dout  = mem[raddr_reg];

// verilint 257 off
// verilint 280 off
// verilint 548 off
// verilint 193 off
// verilint 529 off

//latch write data
always @(posedge clk)
begin
   if (we)
      mem[waddr] <= din;
   else
      ;
end

//----------------------------------------------------------------------
// Debugging stuff
// verilint translate off
// synopsys translate_off
//simtech modcovoff -bpe
`ifdef DEBUG

wire [WIDTH-1:0] peek_0 = mem[0];
wire [WIDTH-1:0] peek_1 = mem[1];
wire [WIDTH-1:0] peek_2 = mem[2];
wire [WIDTH-1:0] peek_3 = mem[3];
wire [WIDTH-1:0] peek_4 = mem[4];
wire [WIDTH-1:0] peek_5 = mem[5];
wire [WIDTH-1:0] peek_6 = mem[6];
wire [WIDTH-1:0] peek_7 = mem[7];
wire [WIDTH-1:0] peek_8 = mem[8];
wire [WIDTH-1:0] peek_9 = mem[9];
wire [WIDTH-1:0] peek_10 = mem[10];
wire [WIDTH-1:0] peek_11 = mem[11];
wire [WIDTH-1:0] peek_12 = mem[12];
wire [WIDTH-1:0] peek_13 = mem[13];
wire [WIDTH-1:0] peek_14 = mem[14];
wire [WIDTH-1:0] peek_15 = mem[15];

integer i;

task dump;
begin
    $display("========================================");
    $display("Register Array Memory dump.  Width=%0d, Depth=%0d",WIDTH,DEPTH);
    `ifdef VERILOG
    $showscopes;
    `endif
    for (i=0; i<DEPTH; i=i+1) begin
        $display("#%0x: mem(%x)",i,mem[i]);
    end
    $display("========================================");

end
endtask


`endif // DEBUG
// synopsys translate_on
// verilint translate on
//simtech modcovon -bpe


endmodule // niu_regin_sram_model