design/sys/iop/niu/rtl/niu_smx_ff_regfl.v

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//
// OpenSPARC T2 Processor File: niu_smx_ff_regfl.v
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module niu_smx_ff_regfl(
/*AUTOARG*/
   // Outputs
   full, empty, rdata,
   // Inputs
   clk, reset_l, wr, wdata, rd
   );

// synopsys template

parameter DATA_WIDTH= 128;
parameter ADDR_WIDTH= 4;

// fifo if
input                   clk;
input                   reset_l;

input                   wr;
input [DATA_WIDTH-1:0]  wdata;
output                  full;

input                   rd;
output                  empty;
output [DATA_WIDTH-1:0] rdata;

wire [DATA_WIDTH-1:0] mwdata= wdata;
wire [DATA_WIDTH-1:0] mrdata;
wire [DATA_WIDTH-1:0] rdata= mrdata;
wire [ADDR_WIDTH-1:0] mwaddr;
wire [ADDR_WIDTH-1:0] mraddr;
wire mwr;
wire mrd;

niu_smx_ff_ctrl #(ADDR_WIDTH) ctrl(
        .clk            (clk),
        .reset_l        (reset_l),
        .wr             (wr),
        .rd             (rd),
        .full           (full),
        .empty          (empty),
        .mwr            (mwr),
        .mwaddr         (mwaddr[ADDR_WIDTH-1:0]),
        .mrd            (mrd),
        .mraddr         (mraddr[ADDR_WIDTH-1:0])
);


niu_smx_regfl #(DATA_WIDTH,ADDR_WIDTH) regfl(
        .clk            (clk),
        .reset_l        (reset_l),
        .wr             (mwr),
        .addr_wr        (mwaddr[ADDR_WIDTH-1:0]),
        .data_wr        (mwdata[DATA_WIDTH-1:0]),
        .rd             (mrd),
        .addr_rd        (mraddr[ADDR_WIDTH-1:0]),
        .data_rd        (mrdata[DATA_WIDTH-1:0])
);

endmodule

/*
 // if need ram, need to explicitly specify
module niu_smx_ff_66bx16(
);

parameter DATA_WIDTH= 128;
parameter ADDR_WIDTH= 4;

// fifo if
input clk;
input reset_l;

input wr;
input [DATA_WIDTH-1:0] wdata;
output full;

input rd;
output empty;
output [DATA_WIDTH-1:0]rdata;

wire [DATA_WIDTH-1:0] mwdata= wdata;
wire [DATA_WIDTH-1:0] mrdata;
wire [DATA_WIDTH-1:0] rdata= mrdata;

niu_smx_ff_ctrl #(DATA_WIDTH,ADDR_WIDTH) ctrl(
        .clk            (clk),
        .reset_l        (reset_l),
        .wr             (wr),
        .rd             (rd),
        .full           (full),
        .empty          (empty),
        .mwr            (mwr),
        .mwaddr         (mwaddr[ADDR_WIDTH-1:0]),
        .mrd            (mrd),
        .mraddr         (mraddr[ADDR_WIDTH-1:0])
);


niu_smx_regfl regfl(DATA_WIDTH,ADDR_WIDTH) regfl
        .clk            (clk),
        .reset_l        (reset_l),
        .wr             (mwr),
        .addr_wr        (mwaddr[ADDR_WIDTH-1:0]),
        .data_wr        (mwdata[DATA_WIDTH-1:0]),
        .rd             (mrd),
        .addr_rd        (mraddr[ADDR_WIDTH-1:0]),
        .data_rd        (mrdata[DATA_WIDTH-1:0])
);

endmodule
*/