design/sys/iop/niu/rtl/niu_smx_req_sii_cr.v

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// OpenSPARC T2 Processor File: niu_smx_req_sii_cr.v
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module niu_smx_req_sii_cr(
/*AUTOARG*/
   // Outputs
   ocr_avail, bcr_avail,
   // Inputs
   clk, reset_l,
   sii_niu_oqdq, sii_niu_bqdq, o_enq, b_enq
   );

input clk;
input reset_l;

// sii if
input           sii_niu_oqdq;
input           sii_niu_bqdq;

// arb if
input           o_enq;
input           b_enq;
output          ocr_avail;
output          bcr_avail;


reg [4:0] order_cr;
reg [4:0] bypass_cr;

reg sii_niu_oqdq_r, sii_niu_bqdq_r;
always @(posedge clk) begin
  if(!reset_l) begin
    sii_niu_oqdq_r<= `SMX_PD  1'b0;
    sii_niu_bqdq_r<= `SMX_PD  1'b0;
  end
  else begin
    sii_niu_oqdq_r<= `SMX_PD  sii_niu_oqdq;
    sii_niu_bqdq_r<= `SMX_PD  sii_niu_bqdq;
  end
end

wire o_deq= sii_niu_oqdq_r;
wire b_deq= sii_niu_bqdq_r;

wire inc_ocr_n= o_deq & ~o_enq;
wire dec_ocr_n= ~o_deq & o_enq;

wire inc_bcr_n= b_deq & ~b_enq;
wire dec_bcr_n= ~b_deq & b_enq;


        // clamp cr in case over
wire [4:0] inc_order_cr_n= (order_cr==`SMX_SII_MAX_ORD_CR)? `SMX_SII_MAX_ORD_CR :
                                                order_cr + 1'b1;
wire [4:0] dec_order_cr_n= (order_cr==5'h0)? 5'h0 : order_cr - 1'b1;

wire [4:0] inc_bypass_cr_n= (bypass_cr==`SMX_SII_MAX_BYP_CR)? `SMX_SII_MAX_BYP_CR :
                                                bypass_cr + 1'b1;
wire [4:0] dec_bypass_cr_n= (bypass_cr==5'h0)? 5'h0 : bypass_cr - 1'b1;

always @(posedge clk) begin
  if(!reset_l) begin
    order_cr<= `SMX_PD  `SMX_SII_MAX_ORD_CR;
    bypass_cr<= `SMX_PD  `SMX_SII_MAX_BYP_CR;
  end
  else begin
    if(inc_ocr_n) order_cr<= `SMX_PD  inc_order_cr_n;
    else if(dec_ocr_n) order_cr<= `SMX_PD  dec_order_cr_n;
    if(inc_bcr_n) bypass_cr<= `SMX_PD  inc_bypass_cr_n;
    else if(dec_bcr_n) bypass_cr<= `SMX_PD  dec_bypass_cr_n;
  end
end

wire ocr_avail= |order_cr;
wire bcr_avail= |bypass_cr;

endmodule