// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: niu_txc_dmaRegisters.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
/*********************************************************************
* NIU Transmit DMA Registers
* Orignal Author(s): Rahoul Puri
* Copyright (c) 2005 Sun Microsystems, Inc.
* This verilog model is the confidential and proprietary property of
* Sun Microsystems, Inc., and the possession or use of this model
* requires a written license from Sun Microsystems, Inc.
**********************************************************************/
module niu_txc_dmaRegisters (
`include "niu_txc_reg_defines.h"
input Read_DMA0_Register;
input Read_DMA1_Register;
input Read_DMA2_Register;
input Read_DMA3_Register;
input Write_DMA0_Register;
input Write_DMA1_Register;
input Write_DMA2_Register;
input Write_DMA3_Register;
input [27:0] SlaveDataIn;
output [31:0] DMA_Slave_DataOut;
reg [31:0] DMA_Slave_DataOut;
input [3:0] Port0_DMA_List;
input [3:0] Port0_UpdateDMANumber;
input [13:0] Port0_UpdateDMALength;
input [3:0] Port1_DMA_List;
input [3:0] Port1_UpdateDMANumber;
input [13:0] Port1_UpdateDMALength;
input [3:0] Port2_DMA_List;
input [3:0] Port2_UpdateDMANumber;
input [13:0] Port2_UpdateDMALength;
input [3:0] Port3_DMA_List;
input [3:0] Port3_UpdateDMANumber;
input [13:0] Port3_UpdateDMALength;
// DMA Registers Grouped in Banks or Four
output [19:0] DMA0_MaxBurst;
output [19:0] DMA1_MaxBurst;
output [19:0] DMA2_MaxBurst;
output [19:0] DMA3_MaxBurst;
reg [19:0] DMA0_MaxBurst;
reg [19:0] DMA1_MaxBurst;
reg [19:0] DMA2_MaxBurst;
reg [19:0] DMA3_MaxBurst;
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
wire collisionDma0Update;
wire collisionDma1Update;
wire collisionDma2Update;
wire collisionDma3Update;
wire [13:0] writeAddress;
reg [13:0] dma0LengthUpdate;
reg [13:0] dma1LengthUpdate;
reg [13:0] dma2LengthUpdate;
reg [13:0] dma3LengthUpdate;
/*--------------------------------------------------------------*/
// Parameters and Defines
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/
assign readDMAregister = (Read_DMA3_Register | Read_DMA2_Register
Read_DMA1_Register | Read_DMA0_Register
assign readIndex = {Read_DMA3_Register, Read_DMA2_Register,
Read_DMA1_Register, Read_DMA0_Register
assign readAddress = {dmaReadIndex, SlaveAddr[11:2], 2'h0};
case (readIndex) // synopsys parallel_case
/* 0in < case -parallel */
4'h1: dmaReadIndex = 2'h0;
4'h2: dmaReadIndex = 2'h1;
4'h4: dmaReadIndex = 2'h2;
4'h8: dmaReadIndex = 2'h3;
default: dmaReadIndex = 2'hx;
assign writeDMAregister = (Write_DMA3_Register | Write_DMA2_Register
Write_DMA1_Register | Write_DMA0_Register
assign writeIndex = {Write_DMA3_Register, Write_DMA2_Register,
Write_DMA1_Register, Write_DMA0_Register
assign writeAddress = {dmaWriteIndex, SlaveAddr[11:2], 2'h0};
case (writeIndex) // synopsys parallel_case
/* 0in < case -parallel */
4'h1: dmaWriteIndex = 2'h0;
4'h2: dmaWriteIndex = 2'h1;
4'h4: dmaWriteIndex = 2'h2;
4'h8: dmaWriteIndex = 2'h3;
default: dmaWriteIndex = 2'hx;
/*--------------------------------------------------------------*/
// TXC DMA 0 PIO Read & Write Registers
/*--------------------------------------------------------------*/
assign dma0Select = {Port3_DMA_List[0], Port2_DMA_List[0],
Port1_DMA_List[0], Port0_DMA_List[0]};
assign dma0Select = {2'h0, Port1_DMA_List[0], Port0_DMA_List[0]};
always @(dma0Select or Port3_ClrMaxBurst
or Port2_ClrMaxBurst or Port1_ClrMaxBurst or Port0_ClrMaxBurst
always @(dma0Select or Port1_ClrMaxBurst or Port0_ClrMaxBurst)
casex(dma0Select) // Synopsys full_case parallel_case
4'bxxx1: clrNewMaxBurstDMA0 = Port0_ClrMaxBurst;
4'bxx10: clrNewMaxBurstDMA0 = Port1_ClrMaxBurst;
4'bx100: clrNewMaxBurstDMA0 = Port2_ClrMaxBurst;
4'b1000: clrNewMaxBurstDMA0 = Port3_ClrMaxBurst;
default: clrNewMaxBurstDMA0 = 1'b0;
always @(dma0Select or Port3_UpdateDMA
or Port2_UpdateDMA or Port1_UpdateDMA or Port0_UpdateDMA
always @(dma0Select or Port1_UpdateDMA or Port0_UpdateDMA)
casex(dma0Select) // Synopsys full_case parallel_case
4'bxxx1: updateDMA0Strobe = Port0_UpdateDMA;
4'bxx10: updateDMA0Strobe = Port1_UpdateDMA;
4'bx100: updateDMA0Strobe = Port2_UpdateDMA;
4'b1000: updateDMA0Strobe = Port3_UpdateDMA;
default: updateDMA0Strobe = 1'b0;
always @(dma0Select or Port3_UpdateDMANumber
or Port2_UpdateDMANumber or Port1_UpdateDMANumber
always @(dma0Select or Port1_UpdateDMANumber or Port0_UpdateDMANumber)
casex(dma0Select) // Synopsys full_case parallel_case
4'bxxx1: dma0Valid = Port0_UpdateDMANumber[0];
4'bxx10: dma0Valid = Port1_UpdateDMANumber[0];
4'bx100: dma0Valid = Port2_UpdateDMANumber[0];
4'b1000: dma0Valid = Port3_UpdateDMANumber[0];
default: dma0Valid = 1'b0;
always @(dma0Select or Port3_UpdateDMALength
or Port2_UpdateDMALength or Port1_UpdateDMALength
always @(dma0Select or Port1_UpdateDMALength or Port0_UpdateDMALength)
casex(dma0Select) // Synopsys full_case parallel_case
4'bxxx1: dma0LengthUpdate = Port0_UpdateDMALength;
4'bxx10: dma0LengthUpdate = Port1_UpdateDMALength;
4'bx100: dma0LengthUpdate = Port2_UpdateDMALength;
4'b1000: dma0LengthUpdate = Port3_UpdateDMALength;
default: dma0LengthUpdate = 14'h0;
assign dma0Update = updateDMA0Strobe & dma0Valid;
assign collisionDma0Update = (dma0Update
(({SlaveAddr[11:2], 2'h0} == `DMA_LENGTH)
Read_DMA0_Register && SlaveStrobe)
always @ (posedge SysClk)
dma0_Length <= #`SD SlaveDataIn[27:0];
else if (collisionDma0Update)
dma0_Length <= #`SD {14'h0, dma0LengthUpdate};
dma0_Length <= #`SD ((dma0_Length + {14'h0, dma0LengthUpdate})
assign setNewMaxBurstDMA0 = (({SlaveAddr[11:2], 2'h0} == `DMA_MAXBURST)
Write_DMA0_Register && SlaveStrobe);
always @ (posedge SysClk)
if (!Reset_L) DMA0_NewMaxBurst <= 1'b0;
else if (setNewMaxBurstDMA0) DMA0_NewMaxBurst <= 1'b1;
else if (clrNewMaxBurstDMA0) DMA0_NewMaxBurst <= 1'b0;
/*--------------------------------------------------------------*/
// TXC DMA 1 PIO Read & Write Registers
/*--------------------------------------------------------------*/
assign dma1Select = {Port3_DMA_List[1], Port2_DMA_List[1],
Port1_DMA_List[1], Port0_DMA_List[1]};
assign dma1Select = {2'h0, Port1_DMA_List[1], Port0_DMA_List[1]};
always @(dma1Select or Port3_ClrMaxBurst
or Port2_ClrMaxBurst or Port1_ClrMaxBurst or Port0_ClrMaxBurst
always @(dma1Select or Port1_ClrMaxBurst or Port0_ClrMaxBurst)
casex(dma1Select) // Synopsys full_case parallel_case
4'bxxx1: clrNewMaxBurstDMA1 = Port0_ClrMaxBurst;
4'bxx10: clrNewMaxBurstDMA1 = Port1_ClrMaxBurst;
4'bx100: clrNewMaxBurstDMA1 = Port2_ClrMaxBurst;
4'b1000: clrNewMaxBurstDMA1 = Port3_ClrMaxBurst;
default: clrNewMaxBurstDMA1 = 1'b0;
always @(dma1Select or Port3_UpdateDMA
or Port2_UpdateDMA or Port1_UpdateDMA or Port0_UpdateDMA
always @(dma1Select or Port1_UpdateDMA or Port0_UpdateDMA)
casex(dma1Select) // Synopsys full_case parallel_case
4'bxxx1: updateDMA1Strobe = Port0_UpdateDMA;
4'bxx10: updateDMA1Strobe = Port1_UpdateDMA;
4'bx100: updateDMA1Strobe = Port2_UpdateDMA;
4'b1000: updateDMA1Strobe = Port3_UpdateDMA;
default: updateDMA1Strobe = 1'b0;
always @(dma1Select or Port3_UpdateDMANumber
or Port2_UpdateDMANumber or Port1_UpdateDMANumber
always @(dma1Select or Port1_UpdateDMANumber or Port0_UpdateDMANumber)
casex(dma1Select) // Synopsys full_case parallel_case
4'bxxx1: dma1Valid = Port0_UpdateDMANumber[1];
4'bxx10: dma1Valid = Port1_UpdateDMANumber[1];
4'bx100: dma1Valid = Port2_UpdateDMANumber[1];
4'b1000: dma1Valid = Port3_UpdateDMANumber[1];
default: dma1Valid = 1'b0;
always @(dma1Select or Port3_UpdateDMALength
or Port2_UpdateDMALength or Port1_UpdateDMALength
always @(dma1Select or Port1_UpdateDMALength or Port0_UpdateDMALength)
casex(dma1Select) // Synopsys full_case parallel_case
4'bxxx1: dma1LengthUpdate = Port0_UpdateDMALength;
4'bxx10: dma1LengthUpdate = Port1_UpdateDMALength;
4'bx100: dma1LengthUpdate = Port2_UpdateDMALength;
4'b1000: dma1LengthUpdate = Port3_UpdateDMALength;
default: dma1LengthUpdate = 14'h0;
assign dma1Update = updateDMA1Strobe & dma1Valid;
assign collisionDma1Update = (dma1Update
(({SlaveAddr[11:2], 2'h0} == `DMA_LENGTH)
Read_DMA1_Register && SlaveStrobe)
always @ (posedge SysClk)
dma1_Length <= #`SD SlaveDataIn[27:0];
else if (collisionDma1Update)
dma1_Length <= #`SD {14'h0, dma1LengthUpdate};
dma1_Length <= #`SD ((dma1_Length + {14'h0, dma1LengthUpdate})
assign setNewMaxBurstDMA1 = (({SlaveAddr[11:2], 2'h0} == `DMA_MAXBURST)
Write_DMA1_Register && SlaveStrobe);
always @ (posedge SysClk)
if (!Reset_L) DMA1_NewMaxBurst <= 1'b0;
else if (setNewMaxBurstDMA1) DMA1_NewMaxBurst <= 1'b1;
else if (clrNewMaxBurstDMA1) DMA1_NewMaxBurst <= 1'b0;
/*--------------------------------------------------------------*/
// TXC DMA 2 PIO Read & Write Registers
/*--------------------------------------------------------------*/
assign dma2Select = {Port3_DMA_List[2], Port2_DMA_List[2],
Port1_DMA_List[2], Port0_DMA_List[2]};
assign dma2Select = {2'h0, Port1_DMA_List[2], Port0_DMA_List[2]};
always @(dma2Select or Port3_ClrMaxBurst
or Port2_ClrMaxBurst or Port1_ClrMaxBurst or Port0_ClrMaxBurst
always @(dma2Select or Port1_ClrMaxBurst or Port0_ClrMaxBurst)
casex(dma2Select) // Synopsys full_case parallel_case
4'bxxx1: clrNewMaxBurstDMA2 = Port0_ClrMaxBurst;
4'bxx10: clrNewMaxBurstDMA2 = Port1_ClrMaxBurst;
4'bx100: clrNewMaxBurstDMA2 = Port2_ClrMaxBurst;
4'b1000: clrNewMaxBurstDMA2 = Port3_ClrMaxBurst;
default: clrNewMaxBurstDMA2 = 1'b0;
always @(dma2Select or Port3_UpdateDMA
or Port2_UpdateDMA or Port1_UpdateDMA or Port0_UpdateDMA
always @(dma2Select or Port1_UpdateDMA or Port0_UpdateDMA)
casex(dma2Select) // Synopsys full_case parallel_case
4'bxxx1: updateDMA2Strobe = Port0_UpdateDMA;
4'bxx10: updateDMA2Strobe = Port1_UpdateDMA;
4'bx100: updateDMA2Strobe = Port2_UpdateDMA;
4'b1000: updateDMA2Strobe = Port3_UpdateDMA;
default: updateDMA2Strobe = 1'b0;
always @(dma2Select or Port3_UpdateDMANumber
or Port2_UpdateDMANumber or Port1_UpdateDMANumber
always @(dma2Select or Port1_UpdateDMANumber or Port0_UpdateDMANumber)
casex(dma2Select) // Synopsys full_case parallel_case
4'bxxx1: dma2Valid = Port0_UpdateDMANumber[2];
4'bxx10: dma2Valid = Port1_UpdateDMANumber[2];
4'bx100: dma2Valid = Port2_UpdateDMANumber[2];
4'b1000: dma2Valid = Port3_UpdateDMANumber[2];
default: dma2Valid = 1'b0;
always @(dma2Select or Port3_UpdateDMALength
or Port2_UpdateDMALength or Port1_UpdateDMALength
always @(dma2Select or Port1_UpdateDMALength or Port0_UpdateDMALength)
casex(dma2Select) // Synopsys full_case parallel_case
4'bxxx1: dma2LengthUpdate = Port0_UpdateDMALength;
4'bxx10: dma2LengthUpdate = Port1_UpdateDMALength;
4'bx100: dma2LengthUpdate = Port2_UpdateDMALength;
4'b1000: dma2LengthUpdate = Port3_UpdateDMALength;
default: dma2LengthUpdate = 14'h0;
assign dma2Update = updateDMA2Strobe & dma2Valid;
assign collisionDma2Update = (dma2Update
(({SlaveAddr[11:2], 2'h0} == `DMA_LENGTH)
Read_DMA2_Register && SlaveStrobe)
always @ (posedge SysClk)
dma2_Length <= #`SD SlaveDataIn[27:0];
else if (collisionDma2Update)
dma2_Length <= #`SD {14'h0, dma2LengthUpdate};
dma2_Length <= #`SD ((dma2_Length + {14'h0, dma2LengthUpdate})
assign setNewMaxBurstDMA2 = (({SlaveAddr[11:2], 2'h0} == `DMA_MAXBURST)
Write_DMA2_Register && SlaveStrobe);
always @ (posedge SysClk)
if (!Reset_L) DMA2_NewMaxBurst <= 1'b0;
else if (setNewMaxBurstDMA2) DMA2_NewMaxBurst <= 1'b1;
else if (clrNewMaxBurstDMA2) DMA2_NewMaxBurst <= 1'b0;
/*--------------------------------------------------------------*/
// TXC DMA 3 PIO Read & Write Registers
/*--------------------------------------------------------------*/
assign dma3Select = {Port3_DMA_List[3], Port2_DMA_List[3],
Port1_DMA_List[3], Port0_DMA_List[3]};
assign dma3Select = {2'h0, Port1_DMA_List[3], Port0_DMA_List[3]};
always @(dma3Select or Port3_ClrMaxBurst
or Port2_ClrMaxBurst or Port1_ClrMaxBurst or Port0_ClrMaxBurst
always @(dma3Select or Port1_ClrMaxBurst or Port0_ClrMaxBurst)
casex(dma3Select) // Synopsys full_case parallel_case
4'bxxx1: clrNewMaxBurstDMA3 = Port0_ClrMaxBurst;
4'bxx10: clrNewMaxBurstDMA3 = Port1_ClrMaxBurst;
4'bx100: clrNewMaxBurstDMA3 = Port2_ClrMaxBurst;
4'b1000: clrNewMaxBurstDMA3 = Port3_ClrMaxBurst;
default: clrNewMaxBurstDMA3 = 1'b0;
always @(dma3Select or Port3_UpdateDMA
or Port2_UpdateDMA or Port1_UpdateDMA or Port0_UpdateDMA
always @(dma3Select or Port1_UpdateDMA or Port0_UpdateDMA)
casex(dma3Select) // Synopsys full_case parallel_case
4'bxxx1: updateDMA3Strobe = Port0_UpdateDMA;
4'bxx10: updateDMA3Strobe = Port1_UpdateDMA;
4'bx100: updateDMA3Strobe = Port2_UpdateDMA;
4'b1000: updateDMA3Strobe = Port3_UpdateDMA;
default: updateDMA3Strobe = 1'b0;
always @(dma3Select or Port3_UpdateDMANumber
or Port2_UpdateDMANumber or Port1_UpdateDMANumber
always @(dma3Select or Port1_UpdateDMANumber or Port0_UpdateDMANumber)
casex(dma3Select) // Synopsys full_case parallel_case
4'bxxx1: dma3Valid = Port0_UpdateDMANumber[3];
4'bxx10: dma3Valid = Port1_UpdateDMANumber[3];
4'bx100: dma3Valid = Port2_UpdateDMANumber[3];
4'b1000: dma3Valid = Port3_UpdateDMANumber[3];
default: dma3Valid = 1'b0;
always @(dma3Select or Port3_UpdateDMALength
or Port2_UpdateDMALength or Port1_UpdateDMALength
always @(dma3Select or Port1_UpdateDMALength or Port0_UpdateDMALength)
casex(dma3Select) // Synopsys full_case parallel_case
4'bxxx1: dma3LengthUpdate = Port0_UpdateDMALength;
4'bxx10: dma3LengthUpdate = Port1_UpdateDMALength;
4'bx100: dma3LengthUpdate = Port2_UpdateDMALength;
4'b1000: dma3LengthUpdate = Port3_UpdateDMALength;
default: dma3LengthUpdate = 14'h0;
assign dma3Update = updateDMA3Strobe & dma3Valid;
assign collisionDma3Update = (dma3Update
(({SlaveAddr[11:2], 2'h0} == `DMA_LENGTH)
Read_DMA3_Register && SlaveStrobe)
always @ (posedge SysClk)
dma3_Length <= #`SD SlaveDataIn[27:0];
else if (collisionDma3Update)
dma3_Length <= #`SD {14'h0, dma3LengthUpdate};
dma3_Length <= #`SD ((dma3_Length + {14'h0, dma3LengthUpdate})
assign setNewMaxBurstDMA3 = (({SlaveAddr[11:2], 2'h0} == `DMA_MAXBURST)
Write_DMA3_Register && SlaveStrobe);
always @ (posedge SysClk)
if (!Reset_L) DMA3_NewMaxBurst <= 1'b0;
else if (setNewMaxBurstDMA3) DMA3_NewMaxBurst <= 1'b1;
else if (clrNewMaxBurstDMA3) DMA3_NewMaxBurst <= 1'b0;
/*--------------------------------------------------------------*/
// TXC DMA 0-3 PIO Read & Write Registers
/*--------------------------------------------------------------*/
always @ (posedge SysClk)
DMA_Slave_DataOut <= 32'h0;
else if (readDMAregister)
case (readAddress) // synopsys parallel_case
/* 0in < case -parallel */
`DMA_0_MAXBURST: DMA_Slave_DataOut <= {12'h0, DMA0_MaxBurst};
`DMA_0_LENGTH: DMA_Slave_DataOut <= {4'h0, dma0_Length};
`DMA_1_MAXBURST: DMA_Slave_DataOut <= {12'h0, DMA1_MaxBurst};
`DMA_1_LENGTH: DMA_Slave_DataOut <= {4'h0, dma1_Length};
`DMA_2_MAXBURST: DMA_Slave_DataOut <= {12'h0, DMA2_MaxBurst};
`DMA_2_LENGTH: DMA_Slave_DataOut <= {4'h0, dma2_Length};
`DMA_3_MAXBURST: DMA_Slave_DataOut <= {12'h0, DMA3_MaxBurst};
`DMA_3_LENGTH: DMA_Slave_DataOut <= {4'h0, dma3_Length};
default: DMA_Slave_DataOut <= 32'h0;
DMA_Slave_DataOut <= 32'h0;
always @ (posedge SysClk)
else if (writeDMAregister)
case (writeAddress) // synopsys parallel_case
/* 0in < case -parallel */
`DMA_0_MAXBURST: DMA0_MaxBurst <= SlaveDataIn[19:0];
`DMA_0_LENGTH: wrDMA0_Length <= 1'b1;
`DMA_1_MAXBURST: DMA1_MaxBurst <= SlaveDataIn[19:0];
`DMA_1_LENGTH: wrDMA1_Length <= 1'b1;
`DMA_2_MAXBURST: DMA2_MaxBurst <= SlaveDataIn[19:0];
`DMA_2_LENGTH: wrDMA2_Length <= 1'b1;
`DMA_3_MAXBURST: DMA3_MaxBurst <= SlaveDataIn[19:0];
`DMA_3_LENGTH: wrDMA3_Length <= 1'b1;
/*--------------------------------------------------------------*/
/*--------------------------------------------------------------*/