// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: niu_zcp_macros.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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// ========== Copyright Header End ============================================
/*****************************************************************
* File Name : niu_zcp_macros.v
* Description : It contains ZCP macros,
* Copyright (c) 2020, Sun Microsystems, Inc.
* Sun Proprietary and Confidential
****************************************************************/
module zcp_par_gen (chk_bit_data,din,par);
wire par_temp = ^(din[dwidth-1:0]);
wire par = chk_bit_data ^ par_temp;
//*****************************
//*****************************
module zcp_RegLd (clk,reset,ld,ld_value,we,din,qout);
input [dwidth-1:0] ld_value;
output [dwidth-1:0] qout;
casex({we, ld}) // synopsys parallel_case full_case
/***********************************
* *********************************/
module zcp_RegDff (din,clk,qout);
output [dwidth-1:0] qout;
//*****************************
//*****************************
module zcp_xREG (clk,reset,en,din,qout);
output [dwidth-1:0] qout;
//*****************************
//*****************************
module zcp_xREG2 (clk,reset,reset_value,load,din,qout);
input [dwidth-1:0] reset_value;
output [dwidth-1:0] qout;
/*****************************
*****************************/
module zcp_RegRst (clk,reset,din,qout);
output [dwidth-1:0] qout;
/***********************************
***********************************/
module zcp_counter (reset,clk,ce,count);
output [dwidth-1:0] count;
1'b1: count <= count + 1;
module zcp_ud_cntr (clk,reset,reset_value,inc,dec,count);
input [dwidth-1:0] reset_value;
output [dwidth-1:0] count;
2'b01: count <= count - 1;
2'b10: count <= count + 1;
module zcp_pls_gen2_reg (clk,sig_in,lead,trail);
assign lead = sig_in_reg & ~sig_out;
assign trail= ~sig_in_reg & sig_out;
endmodule // pls_gen2_reg
module zcp_pls_gen2 (clk,sig_in,lead,trail);
assign lead = sig_in & ~sig_out;
assign trail= ~sig_in & sig_out;
endmodule // zcp_pls_gen2
module zcp_pls_gen1 (clk,sig_in,lead);
assign lead = sig_in & ~sig_out;
endmodule // zcp_pls_gen1
module zcp_w1c_ff (clk,reset,set,ld,w1c,w1c_data,q);
wire rst = w1c & w1c_data;
zcp_pls_gen1 zcp_pls_gen1(.clk(clk),.sig_in(set),.lead(set_pls));
2'b11: q <= 0; // rst has hi pri
module zcp_SRFF (clk,reset,set,rst,q);
input reset, clk, set, rst;
module zcp_RSFF (clk,reset,set,rst,q);
input reset, clk, set, rst;
// *************************************************************************
// Copyright (c) 1995 - 2001 Sun Microsystems, Inc.
// All rights reserved. No part of this design may be reproduced stored
// in a retrieval system, or transmitted, in any form or by any means,
// electronic, mechanical, photocopying, recording, or otherwise, without
// prior written permission of Sun Microsystems, Inc.
// Sun Proprietary: Need-To-Know
// *************************************************************************
// Description : A parameterizable register file made using flip flops.
// Warning: Appropriate only for small number of entries.
parameter WIDTH = 16, // Width (# of bits)
ADDR_BITS = 4, // number of address bits
DEPTH = 1<<ADDR_BITS; // number of entries
//======================================================================
// Input/Outputs declarations
//======================================================================
input wr; // Write strobe
input [WIDTH-1:0] d_in; // data in
input [ADDR_BITS-1:0] wr_addr; // write address
input [ADDR_BITS-1:0] rd_addr; // read address
output [WIDTH-1:0] d_out;
reg [WIDTH-1:0] mem [DEPTH-1:0];
assign d_out = mem[rd_addr];
//----------------------------------------------------------------------
// verilint translate off
// synopsys translate_off
wire [WIDTH-1:0] peek_0 = mem[0];
wire [WIDTH-1:0] peek_1 = mem[1];
wire [WIDTH-1:0] peek_2 = mem[2];
wire [WIDTH-1:0] peek_3 = mem[3];
wire [WIDTH-1:0] peek_4 = mem[4];
wire [WIDTH-1:0] peek_5 = mem[5];
wire [WIDTH-1:0] peek_6 = mem[6];
wire [WIDTH-1:0] peek_7 = mem[7];
wire [WIDTH-1:0] peek_8 = mem[8];
wire [WIDTH-1:0] peek_9 = mem[9];
wire [WIDTH-1:0] peek_10 = mem[10];
wire [WIDTH-1:0] peek_11 = mem[11];
wire [WIDTH-1:0] peek_12 = mem[12];
wire [WIDTH-1:0] peek_13 = mem[13];
wire [WIDTH-1:0] peek_14 = mem[14];
wire [WIDTH-1:0] peek_15 = mem[15];
$display("========================================");
$display("Memory dump. Width=%0d, Depth=%0d",WIDTH,DEPTH);
for (i=0; i<DEPTH; i=i+1) begin
$display("#%0x: mem(%x)",i,mem[i]);
$display("========================================");
module zcpfifo_16d (clk,reset,we,wp,din,rp,dout);
reg [WIDTH-1:0] zcpfifo_reg [0:15]; // 16 deep
// vlint flag_empty_statement off
// vlint flag_null_else_statement off
case (we) // synopsys parallel_case full_case infer_mux
1'b1: zcpfifo_reg[wp] <= din;
1'b0: zcpfifo_reg[wp] <= zcpfifo_reg[wp]; // hold
end // always @ (posedge clk)
// vlint flag_empty_statement on
// vlint flag_null_else_statement on
assign dout = zcpfifo_reg[rp];
/*********************************************************
Description : 4 sets of {nand3, nor2, inv, mux2, reg}
***********************************************************/
ND3M1P nand3_3 ( .Z(do_nad[3]), .A(di_nd3[0]), .B(di_nd3[1]), .C(di_nd3[2]) );
ND3M1P nand3_2 ( .Z(do_nad[2]), .A(di_nd2[0]), .B(di_nd2[1]), .C(di_nd2[2]) );
ND3M1P nand3_1 ( .Z(do_nad[1]), .A(di_nd1[0]), .B(di_nd1[1]), .C(di_nd1[2]) );
ND3M1P nand3_0 ( .Z(do_nad[0]), .A(di_nd0[0]), .B(di_nd0[1]), .C(di_nd0[2]) );
NR2M1P nor_3 ( .Z(do_nor[3]), .A(di_nr3[0]), .B(di_nr3[1]) );
NR2M1P nor_2 ( .Z(do_nor[2]), .A(di_nr2[0]), .B(di_nr2[1]) );
NR2M1P nor_1 ( .Z(do_nor[1]), .A(di_nr1[0]), .B(di_nr1[1]) );
NR2M1P nor_0 ( .Z(do_nor[0]), .A(di_nr0[0]), .B(di_nr0[1]) );
N1M1P inv_3 ( .Z(do_inv[3]), .A(di_inv[3]) );
N1M1P inv_2 ( .Z(do_inv[2]), .A(di_inv[2]) );
N1M1P inv_1 ( .Z(do_inv[1]), .A(di_inv[1]) );
N1M1P inv_0 ( .Z(do_inv[0]), .A(di_inv[0]) );
MUX21HM1P mux21_3 ( .Z(do_mux[3]), .A(di_mx3[0]), .B(di_mx3[1]), .S(mx_sel[3]) );
MUX21HM1P mux21_2 ( .Z(do_mux[2]), .A(di_mx2[0]), .B(di_mx2[1]), .S(mx_sel[2]) );
MUX21HM1P mux21_1 ( .Z(do_mux[1]), .A(di_mx1[0]), .B(di_mx1[1]), .S(mx_sel[1]) );
MUX21HM1P mux21_0 ( .Z(do_mux[0]), .A(di_mx0[0]), .B(di_mx0[1]), .S(mx_sel[0]) );
FD2SL2QM1P regtre_3 ( .Q(do_q[3]), .D(di_reg[3]), .CP(clk), .CD(rst_l[3]), .TI(do_q[2]), .TE(se), .LD(wt_ena[3]) );
FD2SL2QM1P regtre_2 ( .Q(do_q[2]), .D(di_reg[2]), .CP(clk), .CD(rst_l[2]), .TI(do_q[1]), .TE(se), .LD(wt_ena[2]) );
FD2SL2QM1P regtre_1 ( .Q(do_q[1]), .D(di_reg[1]), .CP(clk), .CD(rst_l[1]), .TI(do_q[0]), .TE(se), .LD(wt_ena[1]) );
FD2SL2QM1P regtre_0 ( .Q(do_q[0]), .D(di_reg[0]), .CP(clk), .CD(rst_l[0]), .TI(si), .TE(se), .LD(wt_ena[0]) );
N1M1P inv_rst_3( .Z(rst_l[3]), .A(rst[3]) );
N1M1P inv_rst_2( .Z(rst_l[2]), .A(rst[2]) );
N1M1P inv_rst_1( .Z(rst_l[1]), .A(rst[1]) );
N1M1P inv_rst_0( .Z(rst_l[0]), .A(rst[0]) );