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// OpenSPARC T2 Processor File: pcs_lfsr.v
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/**********************************************************************/
/* Project Name : CASSINI */
/* Module Name : PCS 10 ms timer */
/* Description : A LFSR is used to create a 50% duty cycle clock */
/* which has a 4.2 ms cycle time. */
/* Assumptions : none. */
/* Parent module : pcs_link_config.v */
/* Child modules : none. */
/* Author Name : Linda Chen */
/* Date Created : 11/6/97 */
/* Copyright (c) 1994, Sun Microsystems, Inc. */
/* Sun Proprietary and Confidential */
/* Modifications : none yet */
/* Synthesis Notes : delay cells are added to meet hold time given */
/**********************************************************************/
module pcs_lfsr (txclk,timer_override,reset_tx,timer_tick);
wire slow_clk; // ticks every 2.1 ms
reg [17:0] pat; // pseudo random pattern generated by LFSR
wire feedback; // feedback loop to input of LFSR
wire at_end; // to toggle slow clk high for 50% duty cycle
wire nxt_slow_clk; // input to slow clk register
wire [17:0] del_pat; // delay for hold time for lfsr
assign at_end = (pat == 18'h1),
nxt_slow_clk = (reset_tx)? 1'h0 : (at_end)?
** If timer override is asserted the slow clk ticks
** about every 8 txclk ticks.
timer_tick = (timer_override)? (pat[0] & pat[1]): slow_clk;
** 1 + x^1 + x^2 + x^5 + x^19
if (reset_tx) pat <= 18'h1;
// for hold time requirement
DEL2ns_PAT delay_pattern(
pat[5], // ^ feedback, // x^5
pat[2], // ^ feedback, // x^2
pat[1]});// ^ feedback});// x
REG #(1) r_slow_clk(slow_clk,txclk,nxt_slow_clk);