// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: pcs_rx_dpath.v
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// @(#)pcs_rx_dpath.v 1.1G
/**********************************************************************/
/* Project Name : CASSINI */
/* Module Name : PCS Rx Datapath */
/* Description : The PCS Rx datapath contains the four stage */
/* pipeline used to detect special sequences. It */
/* also contains the Decoder block and input */
/* register. A mux exists which selects among */
/* several special characters and encoded data to */
/* to be shipped over the GMII. */
/* Assumptions : none. */
/* Parent module : pcs.v */
/* Child modules : pcs_decoder.v */
/* Author Name : Linda Chen */
/* Date Created : 10/24/96 */
/* Copyright (c) 1994, Sun Microsystems, Inc. */
/* Sun Proprietary and Confidential */
/* Modifications : 12/9/98 : added output ports comma_p,k285_p for */
/* carrier detect generation and sync */
/* Synthesis Notes : none yet */
/**********************************************************************/
module pcs_rx_dpath (rxclk,reset_rx,enable_pci, // inputs
rx_10bdata,rx_d_sel,link_up_rx,
rx_8bdata,kchar,disp_err,dec_err, // outputs
rx_8bdata_p,kchar_p,disp_err_p,dec_err_p,
got_d_linkconf_p,comma_p,k285w1_p,enable_rx);
input rxclk; // 125 MHz rx clock
input reset_rx; // reset synchronized to rx clk
input enable_pci; // PCS enable bit
input [9:0] rx_10bdata; // incoming 10 bits from link
input [2:0] rx_d_sel; // receive data mux to GMII select
input link_up_rx; // link status sychronized to rx clock domain
output [7:0] rxd; // data going onto GMII
output [7:0] rx_8bdata, // data from decoder
rx_8bdata_p, // data from decoder previous stage
output disp_err, // disparity error flag for rx_8bdata
output dec_err, // decoder error flag for rx_8bdata
wire [9:0] rx_10bdec_in; // data bus input to encoder
wire [7:0] nxt_rxd; // rx data bus to MAC
wire enable_rx; // PCS enable synchronized
wire clr; // clear pipeline
wire dec_err_pp,disp_err_pp,got_d_linkconf_pp,comma_pp,k285w1_pp;
assign clr = reset_rx | ~enable_rx | !link_up_rx;
REG #(10) r_in_reg (.qout(rx_10bdec_in),.clk(rxclk),.din(rx_10bdata));
** DECODER - takes whatever comes in and decodes it to an 8 bit value.
** Generates helpful flags for special data characters and k characters.
** Flags disparity and decode errors.
// vlint flag_non_name_based_inst off
pcs_decoder pcs_decoder(rx_10bdec_in,rxclk, // inputs
rx_8bdata_pp,dec_err_pp,disp_err_pp, // outputs
kchar_pp,got_d_linkconf_pp,comma_pp,k285w1_pp);
// vlint flag_non_name_based_inst on
REG #(8) r_8bdata_p (.qout(rx_8bdata_p),.clk(rxclk),.din(rx_8bdata_pp));
REG #(8) r_8bdata (.qout(rx_8bdata),.clk(rxclk),.din(rx_8bdata_p));
REG #(1) r_kchar_p (.qout(kchar_p),.clk(rxclk),.din(kchar_pp));
REG #(1) r_kchar (.qout(kchar),.clk(rxclk),.din(kchar_p));
REG #(1) r_disp_err_p (.qout(disp_err_p),.clk(rxclk),.din(disp_err_pp));
REG #(1) r_disp_err (.qout(disp_err),.clk(rxclk),.din(disp_err_p));
REG #(1) r_dec_err_p (.qout(dec_err_p),.clk(rxclk),.din(dec_err_pp));
REG #(1) r_dec_err (.qout(dec_err),.clk(rxclk),.din(dec_err_p));
REG #(1) r_got_d_linkconf_p(.qout(got_d_linkconf_p),.clk(rxclk),
.din(got_d_linkconf_pp));
REG #(1) r_comma_p(.qout(comma_p),.clk(rxclk),
REG #(1) r_k285w1_p(.qout(k285w1_p),.clk(rxclk),
SYNCREG r_enable_rx (enable_rx,rxclk,enable_pci);
** Output MUX for rx data out
** PCS_RXD_FALSE_CARRIER 3'h2
** PCS_RXD_CRS_EXT_ER 3'h4
MUX6TO1 #(8) rxd_outmux (.dout(nxt_rxd),.sel(rx_d_sel),.D0(8'h0),.D1(8'h55),
.D2(8'hE),.D3(8'hF),.D4(8'h1F),.D5(rx_8bdata));
RREG #(8) r_rxd (.qout(rxd),.clk(rxclk),.rst(clr),.din(nxt_rxd));
projects / OpenSPARC-T2-DV / blob