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// OpenSPARC T2 Processor File: pcs_tx_disparity.v
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// @(#)pcs_tx_disparity.v 1.1G
/**********************************************************************/
/* Project Name : CASSINI */
/* Module Name : PCS Tx Running Disparity Calculator */
/* Description : Calculates new running disparity based on */
/* disparity and incoming data for use by encoder. */
/* Assumptions : none. */
/* Parent module : pcs_decoder.v */
/* Child modules : none. */
/* Author Name : Linda Chen */
/* Date Created : 10/21/96 */
/* Copyright (c) 1994, Sun Microsystems, Inc. */
/* Sun Proprietary and Confidential */
/* Modifications : none yet */
/* Synthesis Notes : none yet */
/**********************************************************************/
module pcs_tx_disparity (reset_tx, txclk,special_char, tx_enc_sel,// inputs
input reset_tx; // reset to initial RD to neg
input txclk; // 125 MHz Tx clk
input special_char; // special char indication
input [3:0] tx_enc_sel; // encoder control
input [7:0] data; // non-encoded data
input RDreg; // running disparity calculated
output RD; // running disparity final
wire rst_reg; // delayed reset by one clock to init rundisp
assign RD = rst_reg ? 1'b0 : rd_fn (special_char,tx_enc_sel,data,RDreg);
REG #(1) r_rstreg( .din(reset_tx), .clk(txclk), .qout(rst_reg) );
case (data[7:0]) //synopsys parallel_case full_case
case (tx_enc_sel) // synopsys parallel_case full_case
`PCS_ENC_K285 : // 4'h0 - K28.5
`PCS_ENC_IDLE2 : // 4'h1 - D16.2
`PCS_ENC_SOP : // 4'h2 - K27.7
`PCS_ENC_T_CHAR : // 4'h4 - K29.7
`PCS_ENC_R_CHAR : // 4'h5 - K23.7
`PCS_ENC_IDLE1 : // 4'h6 - D5.6
`PCS_ENC_H_CHAR : // 4'h7 - K30.7
`PCS_ENC_LINK_CONFA : // 4'h8 - D21.5
`PCS_ENC_LINK_CONFB : // 4'h9 - D2.2
projects / OpenSPARC-T2-DV / blob