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// OpenSPARC T2 Processor File: rxfifo_load.v
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/*************************************************************************
* File Name : rxfifo_load
* Description : It contains physical rxmac fifo and associated control
* logic (read/write pointers).
* Child Module: rxfifo_memory_model
* Copyright (c) 2002, Sun Microsystems, Inc.
* Sun Proprietary and Confidential
* Design Notes: Since 802.3ae says that RxMac should be able to handle
* min IPG == 4 byte times, it is a good idea to have a
* larger rxfifo to combat this temporary phenominum.
*************************************************************************/
rxfifo_wen, // for rxfifo to generate wr_en
rxfifo_dout, // {mac_own_da,tag,64bit data}
rxfifo_g_wr_ptr_rxclk, // to xmac_sync.v
// for signal observation
input rxfifo_wen; // for rxfifo to generate wr_en
input [4:0] rxfifo_g_rd_ptr_sync;
input [3:0] rxfifo_rd_ptr_clk;
output [65:0] rxfifo_dout; // {mac_own_da,tag,64bit data}
output [4:0] rxfifo_g_wr_ptr_rxclk; // to xmac_sync.v
output rxfifo_full_rxclk;
output rxfifo_afull_rxclk;
// for signal observation
output [4:0] rxfifo_wr_ptr_rxclk;
output rxfifo_empty_rxclk;
output rxfifo_overrun_rxclk;
wire [4:0] rxfifo_wr_ptr_rxclk;
// wire [4:0] rxfifo_wr_ptr_plus1_rxclk;
wire [4:0] rxfifo_g_wr_ptr_rxclk;
wire [4:0] rxfifo_rd_ptr_rxclk;
wire rxfifo_wr_en = rxfifo_wen & (~rxfifo_full_rxclk);
// Before the rxfifo overflow bug was found (9/26/00), the signal:
// rxfifo_full_rxclk can not be used to stop rxfifo_wr_en.
// Because it is necessary to let eop and status tag be written
// so that IPP can discard this pkt.
// But now the rxfifo effective depth is reduced to 15 and the
// rxfifo_afull_rxclk is used to generate eop and write to
// rxfifo (one last data entry left), so it is ok to use
// rxfifo_full to block rxfifo_wr_en. -loj (9/27/00)
// In Feb. 10th, 2004, the rxfifo overflow bug shows up again.
// It is caused by adding one more layer of pipeline register
// to add the strip_crc function.
// For this reason, the rxfifo_afull signal has to be extended 1 more.
/* --------------- start rxfifo pointer Management ------------------ */
// Rxfifo read Pointer, rd_ptr from sysclk
g2b_5bit rxfifo_g_rd_ptr_g2b_5bit(.g_cnt(rxfifo_g_rd_ptr_sync),
.b_cnt(rxfifo_rd_ptr_rxclk));
// Rxfifo G Write Pointer, g_wr_ptr to sysclk
g_cntr_5bit rxfifo_g_wr_ptr_rxclk_g_cntr_5bit( .reset(rx_reset),
.g_cnt(rxfifo_g_wr_ptr_rxclk));
g2b_5bit rxfifo_g2b_5bit(.g_cnt(rxfifo_g_wr_ptr_rxclk),
.b_cnt(rxfifo_wr_ptr_rxclk));
//assign rxfifo_wr_ptr_plus1_rxclk = rxfifo_wr_ptr_rxclk + 1;
wire [4:0] rxfifo_empty_space = (rxfifo_wr_ptr_rxclk[4] == rxfifo_rd_ptr_rxclk[4]) ?
16 - ({1'b0,rxfifo_wr_ptr_rxclk[3:0]} - {1'b0,rxfifo_rd_ptr_rxclk[3:0]}):
({1'b0,rxfifo_rd_ptr_rxclk[3:0]} - {1'b0,rxfifo_wr_ptr_rxclk[3:0]});
//wire [4:0] rxfifo_full_space = (rxfifo_wr_ptr_rxclk[4] == rxfifo_rd_ptr_rxclk[4]) ?
// ({1'b0,rxfifo_wr_ptr_rxclk[3:0]} - {1'b0,rxfifo_rd_ptr_rxclk[3:0]}):
// 16 - ({1'b0,rxfifo_rd_ptr_rxclk[3:0]} - {1'b0,rxfifo_wr_ptr_rxclk[3:0]});
wire rxfifo_full_rxclk = (rxfifo_wr_ptr_rxclk[4] == (!rxfifo_rd_ptr_rxclk[4])) &&
(rxfifo_wr_ptr_rxclk[3:0] == rxfifo_rd_ptr_rxclk[3:0]);
//wire rxfifo_afull_rxclk = (rxfifo_wr_ptr_plus1_rxclk[4] == (!rxfifo_rd_ptr_rxclk[4])) &&
// (rxfifo_wr_ptr_plus1_rxclk[3:0] == rxfifo_rd_ptr_rxclk[3:0]);
wire rxfifo_afull_rxclk = rxfifo_empty_space < 3; // 2 empty space left
wire rxfifo_empty_rxclk = (rxfifo_wr_ptr_rxclk[4:0] == rxfifo_rd_ptr_rxclk[4:0]);
wire rxfifo_overrun_rxclk = rxfifo_afull_rxclk & rxfifo_wr_en;
/* --------------- end of rxfifo pointer Management ----------------- */
//***********************************************
//***** Rxfifo and associated control logic *****
//***********************************************
rxfifo_memory_model rxfifo_memory_model(
.wp(rxfifo_wr_ptr_rxclk[3:0]),
.rp(rxfifo_rd_ptr_clk[3:0]),
.dout(rxfifo_dout[65:0]));
module rxfifo_memory_model (rx_clk,reset,wp,rp,we,din,dout);
reg [65:0] rxfifo_mem [0:15]; // 65 bit wide 16 deep
always @ (posedge rx_clk)
case (we) // synopsys parallel_case full_case infer_mux
1'b1: rxfifo_mem[wp] <= din;
1'b0: rxfifo_mem[wp] <= rxfifo_mem[wp];
end // always @ (posedge rx_clk)
assign dout = rxfifo_mem[rp];
endmodule // rxfifo_memory_model