// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: srfifo_load.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// ========== Copyright Header End ============================================
/*************************************************************************
* File Name : srfifo_load
* Copyright (c) 2002, Sun Microsystems, Inc.
* Sun Proprietary and Confidential
*************************************************************************/
srfifo_wr_en, // .srfifo_wr_en(eop) in rx_xmac.v
input srfifo_wr_en; // .srfifo_wr_en(eop) in rx_xmac.v
// vlint flag_input_port_not_connected off
input [4:0] srfifo_rd_ptr_clk;
// vlint flag_input_port_not_connected on
input [`TBITS] srfifo_din; // 24 bits wide
output [`TBITS] srfifo_dout;
output [4:0] srfifo_g_wr_ptr_rxclk;
wire [4:0] srfifo_g_wr_ptr_rxclk;
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
// vlint flag_input_port_not_connected off
wire [4:0] srfifo_wr_ptr_rxclk;
wire [4:0] srfifo_rd_ptr_clk;
// vlint flag_input_port_not_connected on
// vlint flag_net_has_no_load on
// vlint flag_dangling_net_within_module on
/* --------------- start srfifo pointer Management ------------------ */
// srfifo G Write Pointer, g_wr_ptr to sysclk
g_cntr_5bit srfifo_g_wr_ptr_rxclk_g_cntr_5bit(
.g_cnt(srfifo_g_wr_ptr_rxclk));
g2b_5bit srfifo_g2b_5bit(.g_cnt(srfifo_g_wr_ptr_rxclk),
.b_cnt(srfifo_wr_ptr_rxclk));
/* --------------- end of srfifo pointer Management ----------------- */
//***********************************************
//***** srfifo and associated control logic *****
//***********************************************
srfifo_TBITS_memory_model srfifo_TBITS_memory_model(
.wp(srfifo_wr_ptr_rxclk[3:0]),
.rp(srfifo_rd_ptr_clk[3:0]),
.din(srfifo_din[`TBITS]),
.dout(srfifo_dout[`TBITS]));
module srfifo_TBITS_memory_model (rx_clk,reset,wp,rp,we,din,dout);
reg [`TBITS] srfifo_mem [0:15]; // 24 bit wide 16 deep
always @ (posedge rx_clk)
case (we) // synopsys parallel_case full_case infer_mux
1'b1: srfifo_mem[wp] <= din;
1'b0: srfifo_mem[wp] <= srfifo_mem[wp];
end // always @ (posedge rx_clk)
assign dout = srfifo_mem[rp];
endmodule // srfifo_TBITS_memory_model