// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: xpcs_rxio_sync.v
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// ****************************************************************
// Sun Proprietary/Confidential: Internal Use Only
// ****************************************************************
// Design: IB Phy Interface Core
// Block: IB Phy Interface Core Top Level
// Module: xpcs_rxio_sync
// File: xpcs_rxio_sync.v
// Description: This block contains an X12 receive physical
// ------------------------------------------------------------
// ------------------------------------------------------------
// ****************************************************************
output csr_lane_sync_status;
output [3:0] csr_lane_sync_state;
// **********************************************
// Synchronize flush from rx_clk to rx lane clk
// **********************************************
always @ (posedge rx_clk)
assign flush_hold = flush | flush_d;
SYNC_CELL FLUSH_SYNC (.D(flush_hold),
xpcs_rxio_sync_fifo_ptr xpcs_rxio_sync_fifo_ptr (
.w_rst (reset_rxclk_lane),
// 10b/8b decoder for low byte
xpcs_rxio_sync_decoder xpcs_rxio_sync_decode (
.rx_lane_clk (rx_lane_clk),
.rx_lane_reset (reset_rxclk_lane),
.special (special_deskew),
// Synchronization State Machine
xpcs_rxio_sync_sm xpcs_rxio_sync_sm (
.rx_lane_clk (rx_lane_clk),
.rx_signal_detect (rx_signal_detect),
.rx_lane_reset (reset_rxclk_lane),
.byte_deskew (byte_deskew), // Before synchronization on lane clock
.special_deskew (special_deskew),
.error_deskew (error_deskew),
.state (csr_lane_sync_state),
.csr_lane_sync_status (csr_lane_sync_status));
// deskew fifo for low byte stream
xpcs_rxio_sync_deskew_fifo xpcs_rxio_sync_deskew_fifo (
.w_rst (reset_rxclk_lane | flush_sync),
.w_byte (byte_deskew), // Before synchronization on lane clock
.w_special (special_deskew),
.r_ptr (r_ptr), // read ptr synchronized to rx_clk
.byte (byte_out), // data synchronized to rx_clk