design/sys/iop/pcie_common/rtl/dmu_csrtool_enable_all.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: dmu_csrtool_enable_all.h
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* otherwise unspecified.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
*
* ========== Copyright Header End ============================================
*/
`define FIRE_DAEMON_TIMEOUT 1000

`define FIRE_DLC_CRU_A_DAEMON
`define FIRE_DLC_CRU_A_OMNI
// `define FIRE_DLC_CRU_B_DAEMON
// `define FIRE_DLC_CRU_B_OMNI
`define FIRE_DLC_ILU_CIB_A_DAEMON
`define FIRE_DLC_ILU_CIB_A_OMNI
// `define FIRE_DLC_ILU_CIB_B_DAEMON
// `define FIRE_DLC_ILU_CIB_B_OMNI
`define FIRE_DLC_IMU_EQS_A_DAEMON
`define FIRE_DLC_IMU_EQS_A_OMNI
// `define FIRE_DLC_IMU_EQS_B_DAEMON
// `define FIRE_DLC_IMU_EQS_B_OMNI
`define FIRE_DLC_IMU_ICS_A_DAEMON
`define FIRE_DLC_IMU_ICS_A_OMNI
// `define FIRE_DLC_IMU_ICS_B_DAEMON
// `define FIRE_DLC_IMU_ICS_B_OMNI
`define FIRE_DLC_IMU_ISS_A_DAEMON
`define FIRE_DLC_IMU_ISS_A_OMNI
// `define FIRE_DLC_IMU_ISS_B_DAEMON
// `define FIRE_DLC_IMU_ISS_B_OMNI
`define FIRE_DLC_IMU_RDS_INTX_A_DAEMON
`define FIRE_DLC_IMU_RDS_INTX_A_OMNI
// `define FIRE_DLC_IMU_RDS_INTX_B_DAEMON
// `define FIRE_DLC_IMU_RDS_INTX_B_OMNI
`define FIRE_DLC_IMU_RDS_MESS_A_DAEMON
`define FIRE_DLC_IMU_RDS_MESS_A_OMNI
// `define FIRE_DLC_IMU_RDS_MESS_B_DAEMON
// `define FIRE_DLC_IMU_RDS_MESS_B_OMNI
`define FIRE_DLC_IMU_RDS_MSI_A_DAEMON
`define FIRE_DLC_IMU_RDS_MSI_A_OMNI
// `define FIRE_DLC_IMU_RDS_MSI_B_DAEMON
// `define FIRE_DLC_IMU_RDS_MSI_B_OMNI
`define FIRE_DLC_MMU_CSR_A_DAEMON
`define FIRE_DLC_MMU_CSR_A_OMNI
// `define FIRE_DLC_MMU_CSR_B_DAEMON
// `define FIRE_DLC_MMU_CSR_B_OMNI
`define FIRE_DLC_PSB_A_DAEMON
`define FIRE_DLC_PSB_A_OMNI
// `define FIRE_DLC_PSB_B_DAEMON
// `define FIRE_DLC_PSB_B_OMNI
`define FIRE_DLC_TSB_A_DAEMON
`define FIRE_DLC_TSB_A_OMNI
// `define FIRE_DLC_TSB_B_DAEMON
// `define FIRE_DLC_TSB_B_OMNI
`define FIRE_JLC_CSR_JCS_JCS_DAEMON
`define FIRE_JLC_CSR_JCS_JCS_OMNI
`define FIRE_PLC_TLU_CTB_LPR_A_DAEMON
`define FIRE_PLC_TLU_CTB_LPR_A_OMNI
`define FIRE_PLC_TLU_CTB_LPR_B_DAEMON
`define FIRE_PLC_TLU_CTB_LPR_B_OMNI
`define FIRE_PLC_TLU_CTB_TLR_A_DAEMON
`define FIRE_PLC_TLU_CTB_TLR_A_OMNI
`define FIRE_PLC_TLU_CTB_TLR_B_DAEMON
`define FIRE_PLC_TLU_CTB_TLR_B_OMNI