design/sys/iop/pcie_common/rtl/pcie_common_srq.v

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: pcie_common_srq.v
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// GNU General Public License for more details.
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module pcie_common_srq (
                        clk,
                        rst_l,
                        enq,
                        deq,
                        di,
                        do,
                        empty,
                        full,
                        afull
                        );

// ----------------------------------------------------------------------------
// Parameters
// ----------------------------------------------------------------------------
  parameter     QD = 4,                         // queue depth
                QW = 8;                         // queue width

// ----------------------------------------------------------------------------
// Ports
// ----------------------------------------------------------------------------
  input                 clk;                    // clock
  input                 rst_l;                  // reset

  input                 enq;                    // enqueue
  input                 deq;                    // dequeue

  input  [QW-1:0]       di;                     // data in

  output [QW-1:0]       do;                     // data out

  output                empty;                  // empty
  output                full;                   // full
  output                afull;                  // almost full

// ----------------------------------------------------------------------------
// Variables
// ----------------------------------------------------------------------------

  wire [QW-1:0]         do;
  wire                  empty;
  wire                  full;
  wire                  afull;

  wire [QD-1:0]         vld;
  wire [QD-1:0]         ld;
  wire [QD-2:0]         ds;

// ----------------------------------------------------------------------------
// Zero In Checkers
// ----------------------------------------------------------------------------

  //0in fifo -enq enq -deq deq -depth QD -enq_data di -deq_data do

// ----------------------------------------------------------------------------
// Instantiations
// ----------------------------------------------------------------------------

  pcie_common_srq_qdp #(QD, QW) qdp (
                                     .clk       (clk),
                                     .rst_l     (rst_l),
                                     .ld        (ld),
                                     .ds        (ds),
                                     .di        (di),
                                     .do        (do)
                                     );

  pcie_common_srq_qcp #(QD)     qcp (
                                     .clk       (clk),
                                     .rst_l     (rst_l),
                                     .enq       (enq),
                                     .deq       (deq),
                                     .ld        (ld),
                                     .ds        (ds),
                                     .vld       (vld)
                                     );

  pcie_common_srq_qci #(QD)     qci (
                                     .vld       (vld),
                                     .empty     (empty),
                                     .full      (full),
                                     .afull     (afull)
                                     );

endmodule // pcie_common_srq