design/sys/iop/rdp/synopsys/script/user_cfg.scr

source -echo -verbose $dv_root/design/sys/synopsys/script/project_io_cfg.scr

set rtl_files {\
libs/cl/cl_rtl_ext.v
libs/cl/cl_a1/cl_a1.behV
libs/cl/cl_u1/cl_u1.behV
libs/cl/cl_dp1/cl_dp1.behV
libs/cl/cl_sc1/cl_sc1.behV
libs/cl/cl_mc1/cl_mc1.v

libs/clk/rtl/clkgen_rdp_io.v  \
libs/clk/rtl/clkgen_rdp_io2x.v \

libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v
libs/clk/n2_clk_pgrid_cust_l/n2_clk_rdp_io_cust/rtl/n2_clk_rdp_io_cust.v
libs/clk/n2_clk_pgrid_cust_l/n2_clk_rdp_io2x_cust/rtl/n2_clk_rdp_io2x_cust.v

libs/n2sram/dp/n2_niu_dp_256x152s_cust_l/n2_niu_dp_256x152s_cust/rtl/n2_niu_dp_256x152s_cust.v

design/sys/iop/niu/rtl/df1.v \
design/sys/iop/niu/rtl/dffe.v \
design/sys/iop/niu/rtl/dffr.v \
design/sys/iop/niu/rtl/dffre.v \

design/sys/iop/niu/rtl/niu_pio_virt_decode.v \
design/sys/iop/niu/rtl/niu_pio_accepted_sm.v \
design/sys/iop/niu/rtl/niu_pio_fifo16d.v \
design/sys/iop/niu/rtl/niu_rw_ctl.v \
design/sys/iop/niu/rtl/niu_pio_regs.v \
design/sys/iop/niu/rtl/niu_pio_slv_decoder.v \
design/sys/iop/niu/rtl/niu_pio_fzc_slv_decoder.v \
design/sys/iop/niu/rtl/niu_pio_vdmc_decoder.v \
design/sys/iop/niu/rtl/niu_pio_ldgim_decoder.v \
design/sys/iop/niu/rtl/niu_pio_ldsv_decoder.v \
design/sys/iop/niu/rtl/niu_pio_imask0_decoder.v \
design/sys/iop/niu/rtl/niu_pio_imask1_decoder.v \
design/sys/iop/niu/rtl/niu_pio_decoder_6to64.v \
design/sys/iop/niu/rtl/niu_pio_rw_sm.v \
design/sys/iop/niu/rtl/niu_pio_ic.v \
design/sys/iop/niu/rtl/niu_pio_ldgn2group.v \
design/sys/iop/niu/rtl/niu_pio_scheduler64.v \
design/sys/iop/niu/rtl/niu_pio_ig_sm.v \
design/sys/iop/niu/rtl/niu_req_mux.v \
design/sys/iop/niu/rtl/niu_daisy_chain.v \
design/sys/iop/niu/rtl/niu_gnt_encoder.v \
design/sys/iop/niu/rtl/niu_pio_macros.v \
design/sys/iop/niu/rtl/niu_pio_debug.v \
design/sys/iop/niu/rtl/niu_pio_clkbuf.v \
design/sys/iop/niu/rtl/niu_pio_reset.v \
design/sys/iop/niu/rtl/niu_pio.v \

design/sys/iop/niu/rtl/niu_mb4.v \
design/sys/iop/niu/rtl/niu_rdmc_pio_if.v \
design/sys/iop/niu/rtl/niu_rdmc_encode_32.v \
design/sys/iop/niu/rtl/niu_rdmc_pri_encode_32.v \
design/sys/iop/niu/rtl/niu_rdmc_barrel_shl_32.v \
design/sys/iop/niu/rtl/niu_rdmc_cache_acc_ctrl.v \
design/sys/iop/niu/rtl/niu_rdmc_desp_acc_ctrl.v \
design/sys/iop/niu/rtl/niu_rdmc_shadow_ram_ctrl.v \
design/sys/iop/niu/rtl/niu_rdmc_rcr_acc_ctrl.v \
design/sys/iop/niu/rtl/niu_rdmc_rr_arbiter.v \
design/sys/iop/niu/rtl/niu_rdmc_wr_dp_sm.v \
design/sys/iop/niu/rtl/niu_rdmc_wr_sched.v \
design/sys/iop/niu/rtl/niu_rdmc_wr_dp.v \
design/sys/iop/niu/rtl/niu_rdmc_dp_master.v \
design/sys/iop/niu/rtl/niu_rdmc_buf_manager.v \
design/sys/iop/niu/rtl/niu_rdmc_fetch_desp_sm.v \
design/sys/iop/niu/rtl/niu_rdmc_chnl_pio_if.v \
design/sys/iop/niu/rtl/niu_rdmc_rcr_manager.v \
design/sys/iop/niu/rtl/niu_rdmc_chnl_master.v \
design/sys/iop/niu/rtl/niu_rdmc_clk_buf.v \
design/sys/iop/niu/rtl/niu_rdmc.v \
design/sys/iop/niu/rtl/niu_ram_256_148.v \
design/sys/iop/niu/rtl/niu_ram_256x148.v \

design/sys/iop/niu/rtl/debug.v \
design/sys/iop/niu/rtl/niu_pio_ucb.v \
design/sys/iop/niu/rtl/niu_pio_ucb_in32.v \
design/sys/iop/niu/rtl/niu_pio_ucb_out32.v \
design/sys/iop/rdp/rtl/rdp_dmoreg.v \
design/sys/iop/rdp/rtl/rdp_n2_efuhdr4a_ctl.v \
design/sys/iop/rdp/rtl/rdp_n2_efuhdr4a_l1clkhdr_ctl_macro.v \
design/sys/iop/rdp/rtl/rdp_n2_efuhdr4a_msff_ctl_macro__en_1__width_22.v \
design/sys/iop/rdp/rtl/rdp_n2_efuhdr4a_msff_ctl_macro__en_1__width_5.v \
design/sys/iop/rdp/rtl/rdp_n2_efuhdr4a_msff_ctl_macro__width_4.v \
design/sys/iop/rdp/rtl/rdp_n2_efuhdr4b_ctl.v \
design/sys/iop/rdp/rtl/rdp_n2_efuhdr4b_l1clkhdr_ctl_macro.v \
design/sys/iop/rdp/rtl/rdp_n2_efuhdr4b_msff_ctl_macro__en_1__width_22.v \
design/sys/iop/rdp/rtl/rdp_n2_efuhdr4b_msff_ctl_macro__en_1__width_5.v \
design/sys/iop/rdp/rtl/rdp_n2_efuhdr4b_msff_ctl_macro__width_4.v \
design/sys/iop/rdp/rtl/rdp_n2_efuhdr4a_spare_ctl_macro__num_4.v \
design/sys/iop/rdp/rtl/rdp_n2_efuhdr4b_spare_ctl_macro__num_4.v \
design/sys/iop/rdp/rtl/rdp_clkgen_rdp_io.v \
design/sys/iop/rdp/rtl/rdp_clkgen_rdp_io2x.v \
design/sys/iop/rdp/rtl/rdp.v \

}

set link_library [concat $link_library \
   dw_foundation.sldb \
]


set mix_files {}
set top_module rdp

set include_paths {\
}

set black_box_libs {}
set black_box_designs {}
set mem_libs {}

set dont_touch_modules {\
n2_niu_dp_256x152s_cust \
}

set compile_effort   "medium"

set compile_flatten_all 1

set compile_no_new_cells_at_top_level false

set default_clk cmp_gclk_c0_rdp
set default_clk_freq  1500
set default_setup_skew  0.0
set default_hold_skew  0.0
set default_clk_transition  0.05
set clk_list {                        \
                { cmp_gclk_c0_rdp    1500.0   0.000   0.000   0.05}        \
}

set ideal_net_list {}
set false_path_list {}
set enforce_input_fanout_one     0
set allow_outport_drive_innodes  1
set skip_scan            0
set add_lockup_latch     false
set chain_count          1
set scanin_port_list     {}
set scanout_port_list    {}
set scanenable_port      global_shift_enable
set has_test_stub        1
set scanenable_pin       test_stub_no_bist/se
set long_chain_so_0_net  long_chain_so_0
set short_chain_so_0_net short_chain_so_0
set so_0_net             so_0
set insert_extra_lockup_latch 0
set extra_lockup_latch_clk_list {}