design/sys/iop/rtx/rtl/rtx_n2_efuhdr7_p0_l1clkhdr_ctl_macro.v

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// OpenSPARC T2 Processor File: rtx_n2_efuhdr7_p0_l1clkhdr_ctl_macro.v
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// any PARAMS parms go into naming of macro

module rtx_n2_efuhdr7_p0_l1clkhdr_ctl_macro (
  l2clk,
  l1en,
  pce_ov,
  stop,
  se,
  l1clk);


  input l2clk;
  input l1en;
  input pce_ov;
  input stop;
  input se;
  output l1clk;


cl_a1_l1hdr_8x c_0 (


   .l2clk(l2clk),
   .pce(l1en),
   .l1clk(l1clk),
  .se(se),
  .pce_ov(pce_ov),
  .stop(stop)
);


endmodule