// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: rtx_n2_efuhdr7_p1_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
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// ========== Copyright Header End ============================================
module rtx_n2_efuhdr7_p1_ctl (
wire ff_input_all_enable_scanin;
wire ff_input_all_enable_scanout;
wire efu_hdr_write_data_r1;
wire [21:0] sram_read_data;
wire [21:0] received_instr;
wire ff_receiver_instr_slice_scanin;
wire ff_receiver_instr_slice_scanout;
wire ff_sync_sram_data_scanin;
wire ff_sync_sram_data_scanout;
wire ff_sync_read_data_scanin;
wire ff_sync_read_data_scanout;
wire ff_sync_sram_clr_scanin;
wire ff_sync_sram_clr_scanout;
wire ff_sync_sram_wr_scanin;
wire ff_sync_sram_wr_scanout;
wire ff_counter_slice_scanin;
wire ff_counter_slice_scanout;
wire ff_rd_counter_scanin;
wire ff_rd_counter_scanout;
input efu_hdr_write_data;
output hdr_efu_read_data;
output [10:0] hdr_sram_rvalue;
output [10:0] hdr_sram_rid;
input [10:0] sram_hdr_read_data;
assign pce_ov = tcu_pce_ov;
assign stop = tcu_clk_stop;
//l1clkhdr_ctl_macro clkgen_l1clk
rtx_n2_efuhdr7_p1_msff_ctl_macro__library_a1__width_4 ff_input_all_enable
.scan_in(ff_input_all_enable_scanin),
.scan_out(ff_input_all_enable_scanout),
.dout ({efu_hdr_xfer_en_r1,efu_hdr_write_data_r1,efu_hdr_clr_r1,efu_hdr_xfer_en_r2}),
.din ({efu_hdr_xfer_en, efu_hdr_write_data ,efu_hdr_clr, efu_hdr_xfer_en_r1}),
assign efu_instr[21:0] = {instr[20:0],efu_hdr_write_data_r1};
assign sram_read_data[21:0] = {instr[21:11],sram_hdr_read_data[10:0]};
assign received_instr[21:0] = efu_hdr_xfer_en_r1 ? efu_instr[21:0]
: rdcount == 5'd23 ? sync_read
: dispatch_read_data ? ({instr[20:0],1'b0}) : 22'b0;
assign reset_bus[21:0] = {reset_l, reset_l, reset_l, reset_l, reset_l, reset_l,
reset_l, reset_l, reset_l, reset_l, reset_l, reset_l,
reset_l, reset_l, reset_l, reset_l, reset_l, reset_l,
reset_l, reset_l, reset_l, reset_l};
//assign received_instr[21:0] = efu_hdr_xfer_en_r1 ? efu_instr[21:0] :
// (count==5'd6) ? sram_read_data[21:0] :
// dispatch_read_data ? ({instr[20:0],1'b0}) : 22'b0;
//assign load_shift_reg = efu_hdr_xfer_en_r1 | dispatch_read_data;
assign load_shift_reg = efu_hdr_xfer_en_r1 | dispatch_read_data | rdcount == 5'd23;
rtx_n2_efuhdr7_p1_msff_ctl_macro__en_1__library_a1__width_22 ff_receiver_instr_slice
.scan_in(ff_receiver_instr_slice_scanin),
.scan_out(ff_receiver_instr_slice_scanout),
.din (reset_bus[21:0] & received_instr[21:0]),
.en (~reset_l | load_shift_reg),
// generate wr_en after 1 cycle of setup and enable bits are valid
//assign wr_en = (count==5'd7) & sync_instr[11] & sync_instr[0];
assign wr_en = reset_l & (count==5'd7) & ~sync_instr[21];
rtx_n2_efuhdr7_p1_msff_ctl_macro__en_1__library_a1__width_22 ff_sync_sram_data
.scan_in(ff_sync_sram_data_scanin),
.scan_out(ff_sync_sram_data_scanout),
.dout (sync_instr[21:0]),
.din (reset_bus[21:0] & instr[21:0]),
.en (~reset_l | count==5'd8),
rtx_n2_efuhdr7_p1_msff_ctl_macro__en_1__library_a1__width_22 ff_sync_read_data
.scan_in(ff_sync_read_data_scanin),
.scan_out(ff_sync_read_data_scanout),
.din (reset_bus[21:0] & sram_read_data[21:0]),
.en (~reset_l | count==5'd1),
rtx_n2_efuhdr7_p1_msff_ctl_macro__library_a1__width_1 ff_sync_sram_clr
.scan_in(ff_sync_sram_clr_scanin),
.scan_out(ff_sync_sram_clr_scanout),
rtx_n2_efuhdr7_p1_msff_ctl_macro__library_a1__width_1 ff_sync_sram_wr
.scan_in(ff_sync_sram_wr_scanin),
.scan_out(ff_sync_sram_wr_scanout),
assign load_en = (~efu_hdr_xfer_en_r2 & efu_hdr_xfer_en_r1);
assign ld_rd_en = (count==5'd1);
assign reset_count = ( count == 5'd0 );
assign rdreset_count = ( rdcount == 5'd0 );
assign count_in = ~reset_l ? 5'b0 : load_en ? 5'd29 : reset_count ? 5'b0 : ( count - 5'b1);
assign rdcount_in = ~reset_l ? 5'b0 : ld_rd_en ? 5'd23 : rdreset_count ? 5'b0 : (rdcount - 5'b1);
rtx_n2_efuhdr7_p1_msff_ctl_macro__library_a1__width_5 ff_counter_slice
.scan_in(ff_counter_slice_scanin),
.scan_out(ff_counter_slice_scanout),
rtx_n2_efuhdr7_p1_msff_ctl_macro__library_a1__width_5 ff_rd_counter
.scan_in(ff_rd_counter_scanin),
.scan_out(ff_rd_counter_scanout),
//spare_ctl_macro spares (num=4) (
// .scan_in(spares_scanin),
// .scan_out(spares_scanout),
//assign hdr_sram_rvalue[10:0] = instr[10:0];
//assign hdr_sram_rid[10:0] = instr[21:11];
//assign hdr_sram_red_clr = efu_hdr_clr_r1;
//assign hdr_sram_wr_en = |(count[1:0]);
assign hdr_sram_rvalue[10:0] = sync_instr[10:0];
assign hdr_sram_rid[10:0] = {sync_instr[21],1'b0,sync_instr[20:12]};
assign hdr_sram_red_clr = sync_clr;
assign hdr_sram_wr_en = sync_wr;
//assign dispatch_read_data = (count[4:0]>5'd7);
assign dispatch_read_data = (rdcount[4:0] < 5'd23 & rdcount[4:0] != 5'd0);
assign hdr_efu_read_data = instr[21];
assign hdr_efu_xfer_en = dispatch_read_data;
assign ff_input_all_enable_scanin = scan_in;
assign ff_receiver_instr_slice_scanin = ff_input_all_enable_scanout;
assign ff_counter_slice_scanin = ff_receiver_instr_slice_scanout;
assign ff_sync_sram_data_scanin = ff_counter_slice_scanout;
assign ff_sync_read_data_scanin = ff_sync_sram_data_scanout;
assign ff_sync_sram_clr_scanin = ff_sync_read_data_scanout;
assign ff_sync_sram_wr_scanin = ff_sync_sram_clr_scanout;
assign ff_rd_counter_scanin = ff_sync_sram_wr_scanout;
assign scan_out = ff_rd_counter_scanout;
//assign spares_scanin = ff_rd_counter_scanout ;
//assign scan_out = spares_scanout ;
// any PARAMS parms go into naming of macro
module rtx_n2_efuhdr7_p1_msff_ctl_macro__library_a1__width_4 (
assign fdin[3:0] = din[3:0];
// any PARAMS parms go into naming of macro
module rtx_n2_efuhdr7_p1_msff_ctl_macro__en_1__library_a1__width_22 (
assign fdin[21:0] = (din[21:0] & {22{en}}) | (dout[21:0] & ~{22{en}});
// any PARAMS parms go into naming of macro
module rtx_n2_efuhdr7_p1_msff_ctl_macro__library_a1__width_1 (
assign fdin[0:0] = din[0:0];
// any PARAMS parms go into naming of macro
module rtx_n2_efuhdr7_p1_msff_ctl_macro__library_a1__width_5 (
assign fdin[4:0] = din[4:0];
projects / OpenSPARC-T2-DV / blob