// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: sio_old_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
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// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// choice is available it will apply instead, Sun elects to use only
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// ========== Copyright Header End ============================================
wire dff_in_sol0_scanout;
wire eff_perr_sol1_scanin;
wire eff_perr_sol1_scanout;
wire eff_ue0_sol2_scanin;
wire eff_ue0_sol2_scanout;
wire eff_ue1_sol2_scanin;
wire eff_ue1_sol2_scanout;
wire eff_ue2_sol2_scanin;
wire eff_ue2_sol2_scanout;
wire eff_ue3_sol2_scanin;
wire eff_ue3_sol2_scanout;
wire [5:0] hqsyndromeout;
wire [5:0] ctag_syndrome;
wire eff_jtagsr_h_scanin;
wire eff_jtagsr_h_scanout;
wire [63:0] in_jtag_temp;
input [31:0] din; // from l2b...goes to mbist muxes and flops for sol0 stage
input olc_oldue_check_clrerr; // start of parity checking -- clear out any prior error state
input olc_oldue_check_en; // flop-enable for the parity error accumulator
input [3:0] olc_oldue_wr_en; // write enable for UE fifo
input [1:0] olc_oldue_rd_addr; // read pointer for UE fifo
output oldhq_dout_r_bit; // header out {read}
output oldhq_dout_s_bit; // header out {source=dmu}
input [33:0] olddq0_dout; // least significant bits of data cycle
input [33:0] olddq1_dout; // most significant bits of data cycle
input olc_old_selhdr; // select header not data as outputs
input olc_oldue_selfwd; // selects the accumulated ue instead of the set of 4 ue flops
input olc_oldue_pass_late_ue; //
output [64:0] old_opd_data;
input [3:0] olc_oldhq_wr_en; // write-enable
input [ 1:0] olc_oldhq_rd_addr; // read-addr
input [24:0] oldhq_din; // header datain - {ctagecc[5:0], ras_ue, read, dmu, id[15:0]}
input ojc_old_jtagsr_en; // either store the jtag read data or
// shift bits [n:1] into [n-1:0]
// shift in a 0 to the tail [n]
input [1:0] ojc_old_wr_en; // store the jtag read data,
// [1]=push 8Bytes to head(63:32), [0]=push 8Bytes to tail
output old_opcc_jtag; // lsb of jtag shift register
input [4:0] sio_mbi_old_addr;
input [7:0] sio_mbi_old_wdata;
input sio_mbi_oldx_wr_en;
input sio_mbi_oldx_rd_en;
input olc_old_olddqx0_wr_en;
input olc_old_olddqx0_rd_en;
input [4:0] olc_old_olddqx0_waddr;
input [4:0] olc_old_olddqx0_raddr;
input olc_old_olddqx1_wr_en;
input olc_old_olddqx1_rd_en;
input [4:0] olc_old_olddqx1_waddr;
input [4:0] olc_old_olddqx1_raddr;
output old_olddqx0_wr_en;
output old_olddqx0_rd_en;
output [4:0] old_olddqx0_waddr;
output [4:0] old_olddqx0_raddr;
output [33:0] old_olddqx0_din;
output old_olddqx1_wr_en;
output old_olddqx1_rd_en;
output [4:0] old_olddqx1_waddr;
output [4:0] old_olddqx1_raddr;
output [33:0] old_olddqx1_din;
///////////////////////////////////////
// Scan chain connections
///////////////////////////////////////
assign muxtst = tcu_muxtest;
assign test = tcu_dectest;
assign pce_ov = tcu_pce_ov;
assign stop = tcu_clk_stop;
assign olddqx0_din[33:0] = {1'b0, ue, din[31:0]};
assign olddqx1_din[33:0] = {1'b0, ue, din[31:0]};
///////////////////////////////////////
///////////////////////////////////////
sio_old_dp_mux_macro__mux_aope__ports_2__stack_46r__width_46 mx21_mbi_olddqx0 (
.dout ({old_olddqx0_wr_en,
.din0 ({sio_mbi_oldx_wr_en,
{sio_mbi_old_wdata[1:0], {4{sio_mbi_old_wdata[7:0]}}}}),
.din1 ({olc_old_olddqx0_wr_en,
olc_old_olddqx0_waddr[4:0],
olc_old_olddqx0_raddr[4:0],
sio_old_dp_mux_macro__mux_aope__ports_2__stack_46r__width_46 mx21_mbi_olddqx1 (
.dout ({old_olddqx1_wr_en,
.din0 ({sio_mbi_oldx_wr_en,
{sio_mbi_old_wdata[1:0], {4{sio_mbi_old_wdata[7:0]}}}}),
.din1 ({olc_old_olddqx1_wr_en,
olc_old_olddqx1_waddr[4:0],
olc_old_olddqx1_raddr[4:0],
///////////////////////////////////////
///////////////////////////////////////
///////////////////////////////////////
// CAPTURE FLOPS for parity, ue and din
///////////////////////////////////////
sio_old_dp_msff_macro__stack_64c__width_35 dff_in_sol0 (
.scan_in(dff_in_sol0_scanin),
.scan_out(dff_in_sol0_scanout),
.din ({ue, parity[1:0],din[31:0]}),
.dout ({ue_sol0,parity1_sol0, parity0_sol0,in_sol0[31:0]}),
///////////////////////////////////////
// DATA PARITY GENERATION for checking
///////////////////////////////////////
sio_old_dp_prty_macro__width_16 prty_pgen1_sol0 (
sio_old_dp_prty_macro__width_16 prty_pgen0_sol0 (
///////////////////////////////////////
// DATA PARITY COMPARISON
///////////////////////////////////////
sio_old_dp_xor_macro__left_1__stack_4r__width_1 xr2_perr1_sol0 (
sio_old_dp_xor_macro__left_0__stack_4r__width_1 xr2_perr0_sol0 (
///////////////////////////////////////
// DATA Parity error logging CONTROL
///////////////////////////////////////
sio_old_dp_inv_macro__left_0__stack_4r__width_1 inv_passperr_sol0 (
.din (olc_oldue_check_clrerr),
sio_old_dp_nand_macro__left_0__stack_4r__width_1 nd2_olderr_sol0 (
sio_old_dp_nor_macro__left_0__ports_3__stack_4r__width_1 nr3_setperr_sol0 (
sio_old_dp_nand_macro__left_0__ports_2__stack_4r__width_1 nd2_perr_sol0 (
///////////////////////////////////////
// DATA Parity error RESULT FLOP
///////////////////////////////////////
sio_old_dp_msff_macro__left_0__stack_4r__width_1 eff_perr_sol1 (
.scan_in(eff_perr_sol1_scanin),
.scan_out(eff_perr_sol1_scanout),
.en (olc_oldue_check_en),
///////////////////////////////////////
// Uncorrectable Error (UE of datachunks)
///////////////////////////////////////
assign ue0_wren_sol1 = olc_oldue_wr_en[0];
assign ue1_wren_sol1 = olc_oldue_wr_en[1];
assign ue2_wren_sol1 = olc_oldue_wr_en[2];
assign ue3_wren_sol1 = olc_oldue_wr_en[3];
sio_old_dp_msff_macro__left_0__stack_2r__width_1 eff_ue0_sol2 (
.scan_in(eff_ue0_sol2_scanin),
.scan_out(eff_ue0_sol2_scanout),
sio_old_dp_msff_macro__left_0__stack_2r__width_1 eff_ue1_sol2 (
.scan_in(eff_ue1_sol2_scanin),
.scan_out(eff_ue1_sol2_scanout),
sio_old_dp_msff_macro__left_0__stack_2r__width_1 eff_ue2_sol2 (
.scan_in(eff_ue2_sol2_scanin),
.scan_out(eff_ue2_sol2_scanout),
sio_old_dp_msff_macro__left_0__stack_2r__width_1 eff_ue3_sol2 (
.scan_in(eff_ue3_sol2_scanin),
.scan_out(eff_ue3_sol2_scanout),
// 4:1 mux for reading out ue ff
sio_old_dp_mux_macro__left_0__mux_pgdec__ports_4__stack_2r__width_1 mx41_ue41out (
.sel (olc_oldue_rd_addr[1:0]),
// mux_macro mx21_hdrueout (width=1, stack=2r, mux=pgpe, ports=2) (
// .sel0 (olc_oldue_selfwd)
assign ue_out = olc_oldue_pass_late_ue;
///////////////////////////////////////
// OLD DP OUTPUT MUX for data to opd
///////////////////////////////////////
// output mux between header and payload
///////////////////////////////////////
assign old_opd_data[64:32] ={ue_h_l, olddq0_dout[31:0]};
sio_old_dp_or_macro__stack_2l__width_1 or_ue (
sio_old_dp_mux_macro__mux_pgpe__ports_2__stack_32l__width_32 mx21_old_opd_data (
.dout (old_opd_data[31:0]),
.din0 ({hqsyndromeout[5:0], hqctageccout[5:0], hqraseout, 1'b0, hqrout, ue_out, hqtagout[15:0]}),
.din1 ({olddq1_dout[31:0]}),
///////////////////////////////////////
// with an output flop on fifo
// entry : msb:lsb = {ctagecc[5:0], ras_ue,
// read, src, ctag[15:0]}
///////////////////////////////////////
sio_old_dp_mux_macro__mux_pgdec__ports_4__stack_26l__width_26 hqout (
.dout (oldhq_dout[25:0]),
.din0 ({1'b0, mem0[24:0]}),
.din1 ({1'b0, mem1[24:0]}),
.din2 ({1'b0, mem2[24:0]}),
.din3 ({1'b0, mem3[24:0]}),
.sel (olc_oldhq_rd_addr[1:0]),
assign oldhq_dout_r_bit = oldhq_dout[17]; // header out {read}
assign oldhq_dout_s_bit = oldhq_dout[16]; // header out {source=dmu}
assign oldhq_dout_e_bit = oldhq_dout[18]; // header out {E bit = l2[21]}
// FLOP THIS TO LINE UP THE HQ and PAYLOAD QUEUE READ PIPELINE
// and so we can look ahead in the header generation logic
sio_old_dp_msff_macro__stack_32l__width_30 ff_hqout (
.scan_in(ff_hqout_scanin),
.scan_out(ff_hqout_scanout),
.din ({ctag_syndrome[5:0], oldhq_dout[24:19], oldhq_dout[18], oldhq_dout[17], oldhq_dout[15:0]}),
.dout ({hqsyndromeout[5:0], hqctageccout[5:0], hqraseout, hqrout, hqtagout[15:0]}),
assign hqwe0 = olc_oldhq_wr_en[0];
assign hqwe1 = olc_oldhq_wr_en[1];
assign hqwe2 = olc_oldhq_wr_en[2];
assign hqwe3 = olc_oldhq_wr_en[3];
/////////////////////////////////////////////////////
/////////////////////////////////////////////////////
sio_old_dp_msff_macro__stack_26l__width_26 ff_hqmem0 (
.scan_in(ff_hqmem0_scanin),
.scan_out(ff_hqmem0_scanout),
.din ({1'b0, oldhq_din[24:0]}),
.dout ({mem0_unused, mem0[24:0]}),
sio_old_dp_msff_macro__stack_26l__width_26 ff_hqmem1 (
.scan_in(ff_hqmem1_scanin),
.scan_out(ff_hqmem1_scanout),
.din ({1'b0, oldhq_din[24:0]}),
.dout ({mem1_unused, mem1[24:0]}),
sio_old_dp_msff_macro__stack_26l__width_26 ff_hqmem2 (
.scan_in(ff_hqmem2_scanin),
.scan_out(ff_hqmem2_scanout),
.din ({1'b0, oldhq_din[24:0]}),
.dout ({mem2_unused, mem2[24:0]}),
sio_old_dp_msff_macro__stack_26l__width_26 ff_hqmem3 (
.scan_in(ff_hqmem3_scanin),
.scan_out(ff_hqmem3_scanout),
.din ({1'b0, oldhq_din[24:0]}),
.dout ({mem3_unused, mem3[24:0]}),
/////////////////////////////////////////////////////
// SHIFT REGISTERS for JTAG READ
/////////////////////////////////////////////////////
sio_old_dp_msff_macro__stack_32l__width_32 eff_jtagsr_h (
.scan_in(eff_jtagsr_h_scanin),
.scan_out(eff_jtagsr_h_scanout),
sio_old_dp_msff_macro__stack_32l__width_32 eff_jtagsr_l (
.scan_in(eff_jtagsr_scanin),
.scan_out(eff_jtagsr_scanout),
// format we get from l2 for 1st 2 cycle are
// cycle 0 : in_sol0[31:0] = {B0[7:0], B1[7:0], B2[7:0], B3[7:0]}
// cycle 1 : in_sol0[31:0] = {B4[7:0], B5[7:0], B6[7:0], B7[7:0]}
// we[0] : in_jtag[63:32] = in_sol0[31:0] = {B0[7:0], B1[7:0], B2[7:0], B3[7:0]}
// we[1] : in_jtag[31: 0] = in_sol0[31:0] = {B4[7:0], B5[7:0], B6[7:0], B7[7:0]}
// during shift operation, the lsb is removed and everything from msb is shifted
// downward and the msb gets a 0
// in_jtag[63:0] <= {1'b0, out_jtag[63:1]} ;
// assign in_jtag[31: 0] = ojc_old_wr_en[1] ? in_sol0[31:0] : (
// assign in_jtag[63:32] = ojc_old_wr_en[0] ? in_sol0[31:0] : (
// ojc_old_wr_en[1] ? out_jtag[63:32] : {1'b0, outjtag[63:33]);
sio_old_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 mx21_in_jtag_temp (
.dout ({in_jtag[63:32], in_jtag[31:0]}),
.din0 ({in_sol0[31:0], 32'h00000000}),
.din1 ({in_jtag_temp[63:32], in_jtag_temp[31:0]}),
sio_old_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 mx21_in_jtag (
.dout ({in_jtag_temp[63:32], in_jtag_temp[31:0]}),
.din0 ({out_jtag[63:32], in_sol0[31:0]}),
.din1 ({1'b0, out_jtag[63:33], out_jtag[32:1]}),
assign old_opcc_jtag = out_jtag[0];
/////////////////////////////////////////////////////
// CTAG ECC Generation (syndrome generation)
/////////////////////////////////////////////////////
// original c bits generated
// c0 = [0] ^ [1] ^ [3] ^ [4] ^ [6] ^ [8] ^ [10] ^ [11] ^ [13] ^ [15]
// c1 = [0] ^ [2] ^ [3] ^ [5] ^ [6] ^ [9] ^ [10] ^ [12] ^ [13]
// c2 = [1] ^ [2] ^ [3] ^ [7] ^ [8] ^ [9] ^ [10] ^ [14] ^ [15]
// c3 = [4] ^ [5] ^ [6] ^ [7] ^ [8] ^ [9] ^ [10]
// c4 = [11] ^ [12] ^ [13] ^ [14] ^ [15]
// c5 = [0] ^ [1] ^ [2] ^ [3] ^ c0 ^ c1 ^ c2
// s0 = [0] ^ [1] ^ [3] ^ [4] ^ [6] ^ [8] ^ [10] ^ [11] ^ [13] ^ [15] ^ c[0]
// s1 = [0] ^ [2] ^ [3] ^ [5] ^ [6] ^ [9] ^ [10] ^ [12] ^ [13] ^ c[1]
// s2 = [1] ^ [2] ^ [3] ^ [7] ^ [8] ^ [9] ^ [10] ^ [14] ^ [15] ^ c[2]
// s3 = [4] ^ [5] ^ [6] ^ [7] ^ [8] ^ [9] ^ [10] ^ c[3]
// s4 = [11] ^ [12] ^ [13] ^ [14] ^ [15] ^ c[4]
// s5*= [0] ^ [1] ^ [2] ^ [3] ^ [4] ^ [5] ^ [6] ^ [7] ^ [8] ^ [9] ^
// [10] ^ [11] ^ [12] ^ [13] ^ [14] ^ [15] ^ c[0] ^ c[1] ^ c[2] ^ c[3] ^ c[4] ^ c[5]
// note that implementing s5* as (22 terms) would be expensive timing and area wise...
// = [4] ^ [5] ^ [6] ^ [7] ^ [8] ^ [9] ^ [10] ^ [11] ^ [12] ^ [13] ^ [14] ^ [15]
// or s5* = s3 ^ s4 ^ [0] ^ [1] ^ [2] ^ [3] ^ [4]
// ^ c[0] ^ c[1] ^ c[2] ^ c[5]
// we could save some gates
sio_old_dp_prty_macro__width_16 ctag_syndrome0 (
oldhq_dout[0], oldhq_dout[1] , oldhq_dout[3] , oldhq_dout[4] ,
oldhq_dout[6] , oldhq_dout[8] , oldhq_dout[10] , oldhq_dout[11] ,
oldhq_dout[13] , oldhq_dout[15] , oldhq_dout[19]}
sio_old_dp_prty_macro__width_16 ctag_syndrome1 (
oldhq_dout[0], oldhq_dout[2] , oldhq_dout[3] , oldhq_dout[5] ,
oldhq_dout[6] , oldhq_dout[9] , oldhq_dout[10] , oldhq_dout[12] ,
oldhq_dout[13] , oldhq_dout[20]}
sio_old_dp_prty_macro__width_16 ctag_syndrome2 (
oldhq_dout[1], oldhq_dout[2] , oldhq_dout[3] , oldhq_dout[7] ,
oldhq_dout[8] , oldhq_dout[9] , oldhq_dout[10] , oldhq_dout[14] ,
oldhq_dout[15] , oldhq_dout[21]}
sio_old_dp_prty_macro__width_8 ctag_syndrome3 (
.din ({oldhq_dout[4], oldhq_dout[5] , oldhq_dout[6] , oldhq_dout[7] ,
oldhq_dout[8] , oldhq_dout[9] , oldhq_dout[10] , oldhq_dout[22]}
sio_old_dp_prty_macro__width_8 ctag_syndrome4 (
oldhq_dout[11], oldhq_dout[12] , oldhq_dout[13] , oldhq_dout[14] ,
oldhq_dout[15] , oldhq_dout[23]}
sio_old_dp_prty_macro__width_16 ctag_syndrome5 (
oldhq_dout[0], oldhq_dout[1] , oldhq_dout[2] , oldhq_dout[3] ,
oldhq_dout[4] , oldhq_dout[24], oldhq_dout[21], oldhq_dout[20],
oldhq_dout[19], ctag_syndrome[4], ctag_syndrome[3]}
assign dff_in_sol0_scanin = scan_in ;
assign eff_perr_sol1_scanin = dff_in_sol0_scanout ;
assign eff_ue0_sol2_scanin = eff_perr_sol1_scanout ;
assign eff_ue1_sol2_scanin = eff_ue0_sol2_scanout ;
assign eff_ue2_sol2_scanin = eff_ue1_sol2_scanout ;
assign eff_ue3_sol2_scanin = eff_ue2_sol2_scanout ;
assign ff_hqout_scanin = eff_ue3_sol2_scanout ;
assign ff_hqmem0_scanin = ff_hqout_scanout ;
assign ff_hqmem1_scanin = ff_hqmem0_scanout ;
assign ff_hqmem2_scanin = ff_hqmem1_scanout ;
assign ff_hqmem3_scanin = ff_hqmem2_scanout ;
assign eff_jtagsr_h_scanin = ff_hqmem3_scanout ;
assign eff_jtagsr_scanin = eff_jtagsr_h_scanout ;
assign scan_out = eff_jtagsr_scanout ;
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module sio_old_dp_mux_macro__mux_aope__ports_2__stack_46r__width_46 (
// any PARAMS parms go into naming of macro
module sio_old_dp_msff_macro__stack_64c__width_35 (
.so({so[33:0],scan_out}),
// parity macro (even parity)
module sio_old_dp_prty_macro__width_16 (
// xor macro for ports = 2,3
module sio_old_dp_xor_macro__left_1__stack_4r__width_1 (
// xor macro for ports = 2,3
module sio_old_dp_xor_macro__left_0__stack_4r__width_1 (
module sio_old_dp_inv_macro__left_0__stack_4r__width_1 (
// nand macro for ports = 2,3,4
module sio_old_dp_nand_macro__left_0__stack_4r__width_1 (
// nor macro for ports = 2,3
module sio_old_dp_nor_macro__left_0__ports_3__stack_4r__width_1 (
// nand macro for ports = 2,3,4
module sio_old_dp_nand_macro__left_0__ports_2__stack_4r__width_1 (
// any PARAMS parms go into naming of macro
module sio_old_dp_msff_macro__left_0__stack_4r__width_1 (
// any PARAMS parms go into naming of macro
module sio_old_dp_msff_macro__left_0__stack_2r__width_1 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module sio_old_dp_mux_macro__left_0__mux_pgdec__ports_4__stack_2r__width_1 (
// or macro for ports = 2,3
module sio_old_dp_or_macro__stack_2l__width_1 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module sio_old_dp_mux_macro__mux_pgpe__ports_2__stack_32l__width_32 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module sio_old_dp_mux_macro__mux_pgdec__ports_4__stack_26l__width_26 (
// any PARAMS parms go into naming of macro
module sio_old_dp_msff_macro__stack_32l__width_30 (
.so({so[28:0],scan_out}),
// any PARAMS parms go into naming of macro
module sio_old_dp_msff_macro__stack_26l__width_26 (
.so({so[24:0],scan_out}),
// any PARAMS parms go into naming of macro
module sio_old_dp_msff_macro__stack_32l__width_32 (
.so({so[30:0],scan_out}),
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module sio_old_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 (
// parity macro (even parity)
module sio_old_dp_prty_macro__width_8 (