// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: ifu_ftu_cms_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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agc_any_invalidation_req_f,
wire any_invalidation_req_c_l;
wire any_invalidation_req_f_l;
wire rep_way_reg_scanout;
wire ic_enable_reg_scanin;
wire ic_enable_reg_scanout;
wire [7:0] cms_icache_enable;
wire ic_disabled_reg_scanin;
wire ic_disabled_reg_scanout;
input tcu_pce_ov; // scan signals
input [7:0] lsu_ic_enable ;
input lsu_ifu_direct_map;
input [2:0] agd_direct_map_rep_way;
input [7:0] ftp_curr_fetch_thr_f ;
// input [7:0] agd_itlb_valid_f ;
// input agc_qualify_cmiss ;
input ftu_agc_thr0_cmiss_c;
input ftu_agc_thr1_cmiss_c;
input ftu_agc_thr2_cmiss_c;
input ftu_agc_thr3_cmiss_c;
input ftu_agc_thr4_cmiss_c;
input ftu_agc_thr5_cmiss_c;
input ftu_agc_thr6_cmiss_c;
input ftu_agc_thr7_cmiss_c;
input [7:0] cmu_ic_data_parity;
input [39:37] ftu_paddr_unq;
input agc_any_invalidation_req_f;
output ftu_thrx_un_cacheable;
output [2:0] ftu_rep_way;
output [7:0] cms_ic_modified_parity;
output [39:37] ftu_paddr;
assign pce_ov = tcu_pce_ov;
ifu_ftu_cms_ctl_l1clkhdr_ctl_macro clkgen (
///////////////////////////////////////////////////////////
// Generate duplicate miss reset signal from WOB bits. //
///////////////////////////////////////////////////////////
assign itb_tte_cp_c_q = itb_tte_cp_c | itb_bypass_c ;
assign ftu_thrx_un_cacheable = (ftu_paddr[39] | ic_disabled_c | ~itb_tte_cp_c_q) & any_invalidation_req_c_l ;
assign cms_ic_modified_parity[7:0] = (cmu_ic_data_parity[7:0] ^ {8{flip_parity_ff}}) ;
//////////////////////////////////////////////////////////////////
// Replace_way generation. The replace way is just a shifter which
// is shifted whenever a miss is sent to the cmu
//////////////////////////////////////////////////////////////////
assign any_miss = ftu_agc_thr7_cmiss_c | ftu_agc_thr6_cmiss_c | ftu_agc_thr5_cmiss_c |
ftu_agc_thr4_cmiss_c | ftu_agc_thr3_cmiss_c | ftu_agc_thr2_cmiss_c |
ftu_agc_thr1_cmiss_c | ftu_agc_thr0_cmiss_c ;
assign rep_way_inc[2] = (!ftu_rep_way[2] & ftu_rep_way[1] & ftu_rep_way[0]) |
( ftu_rep_way[2] & !ftu_rep_way[0]) |
( ftu_rep_way[2] & !ftu_rep_way[1]) ;
assign rep_way_inc[1] = (ftu_rep_way[1] & !ftu_rep_way[0]) |
(!ftu_rep_way[1] & ftu_rep_way[0]) ;
assign rep_way_inc[0] = (!ftu_rep_way[0]);
assign sel_miss = (any_miss & ~ifu_direct_map_ff);
assign sel_direct_map = ifu_direct_map_ff;
assign sel_hold = ~any_miss & ~ifu_direct_map_ff ;
assign rep_way_in[2:0] = ({3{sel_miss}} & rep_way_inc[2:0] ) |
({3{sel_direct_map}} & agd_direct_map_rep_way[2:0] ) |
({3{sel_hold}} & ftu_rep_way[2:0] ) ;
assign flip_parity = (cmu_l2_err[1] & ~cmu_l2_err[0] & cerer_icl2u_ff) |
(cmu_l2_err[1] & cmu_l2_err[0] & cerer_icl2nd_ff) ;
assign any_invalidation_req_f_l = ~agc_any_invalidation_req_f ;
ifu_ftu_cms_ctl_msff_ctl_macro__width_10 rep_way_reg (
.scan_in(rep_way_reg_scanin),
.scan_out(rep_way_reg_scanout),
.din ({rep_way_in[2:0],flip_parity,lsu_ifu_direct_map,itc_bypass_bf,itb_bypass_f,
any_invalidation_req_f_l,tlu_cerer_icl2u,tlu_cerer_icl2nd}),
.dout ({ftu_rep_way[2:0],flip_parity_ff,ifu_direct_map_ff,itb_bypass_f,itb_bypass_c,
any_invalidation_req_c_l,cerer_icl2u_ff,cerer_icl2nd_ff}),
assign ftu_paddr[39:37] = ftu_paddr_unq[39:37] & {3{any_invalidation_req_c_l}} ;
ifu_ftu_cms_ctl_msff_ctl_macro__width_8 ic_enable_reg (
.scan_in(ic_enable_reg_scanin),
.scan_out(ic_enable_reg_scanout),
.din (lsu_ic_enable[7:0]),
.dout (cms_icache_enable[7:0]),
assign ic_disabled_f = (ftp_curr_fetch_thr_f[0] & ~cms_icache_enable[0] ) |
(ftp_curr_fetch_thr_f[1] & ~cms_icache_enable[1] ) |
(ftp_curr_fetch_thr_f[2] & ~cms_icache_enable[2] ) |
(ftp_curr_fetch_thr_f[3] & ~cms_icache_enable[3] ) |
(ftp_curr_fetch_thr_f[4] & ~cms_icache_enable[4] ) |
(ftp_curr_fetch_thr_f[5] & ~cms_icache_enable[5] ) |
(ftp_curr_fetch_thr_f[6] & ~cms_icache_enable[6] ) |
(ftp_curr_fetch_thr_f[7] & ~cms_icache_enable[7] ) ;
ifu_ftu_cms_ctl_msff_ctl_macro__width_1 ic_disabled_reg (
.scan_in(ic_disabled_reg_scanin),
.scan_out(ic_disabled_reg_scanout),
assign se = tcu_scan_en ;
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
ifu_ftu_cms_ctl_spare_ctl_macro__num_1 spares (
.scan_out(spares_scanout),
assign rep_way_reg_scanin = scan_in ;
assign ic_enable_reg_scanin = rep_way_reg_scanout ;
assign ic_disabled_reg_scanin = ic_enable_reg_scanout ;
assign spares_scanin = ic_disabled_reg_scanout ;
assign scan_out = spares_scanout ;
// any PARAMS parms go into naming of macro
module ifu_ftu_cms_ctl_l1clkhdr_ctl_macro (
// any PARAMS parms go into naming of macro
module ifu_ftu_cms_ctl_msff_ctl_macro__width_10 (
assign fdin[9:0] = din[9:0];
// any PARAMS parms go into naming of macro
module ifu_ftu_cms_ctl_msff_ctl_macro__width_8 (
assign fdin[7:0] = din[7:0];
// any PARAMS parms go into naming of macro
module ifu_ftu_cms_ctl_msff_ctl_macro__width_1 (
assign fdin[0:0] = din[0:0];
// Description: Spare gate macro for control blocks
// Param num controls the number of times the macro is added
// flops=0 can be used to use only combination spare logic
module ifu_ftu_cms_ctl_spare_ctl_macro__num_1 (
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
cl_u1_buf_32x spare0_buf_32x (.in(1'b1),
.out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
.out(spare0_nand3_8x_unused));
cl_u1_inv_8x spare0_inv_8x (.in(1'b1),
.out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
.out(spare0_aoi22_4x_unused));
cl_u1_buf_8x spare0_buf_8x (.in(1'b1),
.out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
.out(spare0_oai22_4x_unused));
cl_u1_inv_16x spare0_inv_16x (.in(1'b1),
.out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
.out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
.out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
.out(spare0_nand2_8x_unused));
cl_u1_buf_16x spare0_buf_16x (.in(1'b1),
.out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
.out(spare0_nor2_16x_unused));
cl_u1_inv_32x spare0_inv_32x (.in(1'b1),
.out(spare0_inv_32x_unused));