// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: lsu_tgd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
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// ========== Copyright Header End ============================================
wire [1:0] w0_16b_parity_m;
wire [1:0] w1_16b_parity_m;
wire [1:0] w2_16b_parity_m;
wire [1:0] w3_16b_parity_m;
wire dff_16b_prty_w01_scanin;
wire dff_16b_prty_w01_scanout;
wire [1:0] w0_16b_parity_b;
wire [1:0] w1_16b_parity_b;
wire dff_16b_prty_w23_scanin;
wire dff_16b_prty_w23_scanout;
wire [1:0] w2_16b_parity_b;
wire [1:0] w3_16b_parity_b;
wire [31:0] tgd_diag_tag01_m;
wire [31:0] tgd_diag_tag23_m;
wire dff_diag_tag_scanin;
wire dff_diag_tag_scanout;
wire [31:0] tgd_diag_tag_b;
wire tte_data_va_27_22_v_;
wire [63:0] ldxa_asi_data_b;
wire [47:3] watchpoint_b;
wire [63:0] bist_mux_data;
input [29:0] dta_rdata_w0_m;
input [29:0] dta_rdata_w1_m;
input [29:0] dta_rdata_w2_m;
input [29:0] dta_rdata_w3_m;
input [3:0] tgc_cache_way_vld_m;
input [3:0] tgc_cache_way_vld2_m;
input [1:0] tgc_way_sel_m;
input [47:3] dcs_watchpoint_m;
input [12:0] dcs_context0_e;
input [12:0] dcs_context1_e;
input dcc_tlb_tag0_read_b;
input dcc_tlb_tag1_read_b;
input dcc_tlb_data_read_b;
input [37:0] tlb_tte_data; // for diag read muxing
input [65:0] tlb_tte_tag; // for diag read muxing
input tlb_tte_u_bit; // for diag read muxing
input tlc_sel_demap_tag_c0;
input tlc_sel_demap_tag_c1;
input [7:0] bist_cmp_data;
output [28:0] dta_rdata_w0_rep;
output [28:0] dta_rdata_w1_rep;
output [28:0] dta_rdata_w2_rep;
output [28:0] dta_rdata_w3_rep;
//output tgd_tte_tag_parity;
//output tgd_tte_data_parity;
output [12:0] tgd_tag_c0;
output [12:0] tgd_tag_c1;
output [63:0] tgd_ldxa_asi_data_b;
output lsu_mbi_tlb_data_cmp;
output lsu_mbi_tlb_cam_hit;
output lsu_mbi_tlb_cam_mhit;
output lsu_mbi_tlb_ctxt0_hit;
output lsu_mbi_tlb_valid;
input tcu_pce_ov; // scan signals
input tcu_se_scancollar_out;
lsu_tgd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0 (
.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
.dout({se,pce_ov,siclk,soclk})
`define TAG_VA_47_28_HI 48
`define TAG_VA_47_28_LO 29
`define TAG_VA_27_22_HI 28
`define TAG_VA_27_22_LO 23
`define TAG_VA_21_16_HI 21
`define TAG_VA_21_16_LO 16
`define TAG_VA_15_13_HI 15
`define TAG_VA_15_13_LO 13
`define DATA_PA_39_28_HI 35
`define DATA_PA_39_28_LO 24
`define DATA_PA_27_22_HI 23
`define DATA_PA_27_22_LO 18
`define DATA_VA_27_22_V 17
`define DATA_PA_21_16_HI 16
`define DATA_PA_21_16_LO 11
`define DATA_VA_21_16_V 10
`define DATA_PA_15_13_HI 9
`define DATA_PA_15_13_LO 7
`define DATA_VA_15_13_V 6
// Parity checking for tag. Tag is available late in M. Flopping all 4 tags into
// B would require 120 flops, but there is not enough time to check 30b parity in M.
// So, generate 16b parity in M and flop that result (2 flops/way). Then finish the
lsu_tgd_dp_prty_macro__width_16 w0_16b_p1 (
.din ({2'b00,dta_rdata_w0_m[29:16]}),
.dout (w0_16b_parity_m[1])
lsu_tgd_dp_prty_macro__width_16 w0_16b_p0 (
.din (dta_rdata_w0_m[15:0]),
.dout (w0_16b_parity_m[0])
lsu_tgd_dp_prty_macro__width_16 w1_16b_p1 (
.din ({2'b00,dta_rdata_w1_m[29:16]}),
.dout (w1_16b_parity_m[1])
lsu_tgd_dp_prty_macro__width_16 w1_16b_p0 (
.din (dta_rdata_w1_m[15:0]),
.dout (w1_16b_parity_m[0])
lsu_tgd_dp_prty_macro__width_16 w2_16b_p1 (
.din ({2'b00,dta_rdata_w2_m[29:16]}),
.dout (w2_16b_parity_m[1])
lsu_tgd_dp_prty_macro__width_16 w2_16b_p0 (
.din (dta_rdata_w2_m[15:0]),
.dout (w2_16b_parity_m[0])
lsu_tgd_dp_prty_macro__width_16 w3_16b_p1 (
.din ({2'b00,dta_rdata_w3_m[29:16]}),
.dout (w3_16b_parity_m[1])
lsu_tgd_dp_prty_macro__width_16 w3_16b_p0 (
.din (dta_rdata_w3_m[15:0]),
.dout (w3_16b_parity_m[0])
lsu_tgd_dp_msff_macro__width_4 dff_16b_prty_w01 (
.scan_in(dff_16b_prty_w01_scanin),
.scan_out(dff_16b_prty_w01_scanout),
.se (tcu_se_scancollar_out),
.din ({w0_16b_parity_m[1:0],w1_16b_parity_m[1:0]}),
.dout ({w0_16b_parity_b[1:0],w1_16b_parity_b[1:0]}),
lsu_tgd_dp_msff_macro__width_4 dff_16b_prty_w23 (
.scan_in(dff_16b_prty_w23_scanin),
.scan_out(dff_16b_prty_w23_scanout),
.se (tcu_se_scancollar_out),
.din ({w2_16b_parity_m[1:0],w3_16b_parity_m[1:0]}),
.dout ({w2_16b_parity_b[1:0],w3_16b_parity_b[1:0]}),
lsu_tgd_dp_xor_macro__width_4 prty_xor (
.din0 ({w3_16b_parity_b[0],w2_16b_parity_b[0],w1_16b_parity_b[0],w0_16b_parity_b[0]}),
.din1 ({w3_16b_parity_b[1],w2_16b_parity_b[1],w1_16b_parity_b[1],w0_16b_parity_b[1]}),
.dout (tag_parity_b[3:0])
lsu_tgd_dp_buff_macro__width_4 prty_buf (
.din (tag_parity_b[3:0]),
.dout ({tgd_w3_parity_b,tgd_w2_parity_b,tgd_w1_parity_b,tgd_w0_parity_b})
// Mux for diagnostic read
lsu_tgd_dp_mux_macro__mux_pgpe__ports_2__stack_32c__width_32 mx_tag_way01 (
.din0 ({dta_rdata_w1_m[29:0],tgc_cache_way_vld_m[1],tgc_cache_way_vld2_m[1]}),
.din1 ({dta_rdata_w0_m[29:0],tgc_cache_way_vld_m[0],tgc_cache_way_vld2_m[0]}),
.sel0 (tgc_way_sel_m[0]),
.dout (tgd_diag_tag01_m[31:0])
lsu_tgd_dp_mux_macro__mux_pgpe__ports_2__stack_32c__width_32 mx_tag_way23 (
.din0 ({dta_rdata_w3_m[29:0],tgc_cache_way_vld_m[3],tgc_cache_way_vld2_m[3]}),
.din1 ({dta_rdata_w2_m[29:0],tgc_cache_way_vld_m[2],tgc_cache_way_vld2_m[2]}),
.sel0 (tgc_way_sel_m[0]),
.dout (tgd_diag_tag23_m[31:0])
lsu_tgd_dp_msff_macro__mux_pgpe__ports_2__stack_32l__width_32 dff_diag_tag (
.scan_in(dff_diag_tag_scanin),
.scan_out(dff_diag_tag_scanout),
.se (tcu_se_scancollar_out),
.din0 (tgd_diag_tag23_m[31:0]),
.din1 (tgd_diag_tag01_m[31:0]),
.sel0 (tgc_way_sel_m[1]),
.dout (tgd_diag_tag_b[31:0]),
lsu_tgd_dp_buff_macro__left_2__rep_1__stack_32c__width_29 buf_tag_w0 (
.din (dta_rdata_w0_m[28:0]),
.dout (dta_rdata_w0_rep[28:0])
lsu_tgd_dp_buff_macro__left_2__rep_1__stack_32c__width_29 buf_tag_w1 (
.din (dta_rdata_w1_m[28:0]),
.dout (dta_rdata_w1_rep[28:0])
lsu_tgd_dp_buff_macro__left_2__rep_1__stack_32c__width_29 buf_tag_w2 (
.din (dta_rdata_w2_m[28:0]),
.dout (dta_rdata_w2_rep[28:0])
lsu_tgd_dp_buff_macro__left_2__rep_1__stack_32c__width_29 buf_tag_w3 (
.din (dta_rdata_w3_m[28:0]),
.dout (dta_rdata_w3_rep[28:0])
lsu_tgd_dp_inv_macro__width_1 inv_sz_mux (
.din (tlb_tte_data[`DATA_VA_27_22_V]),
.dout (tte_data_va_27_22_v_)
lsu_tgd_dp_and_macro__ports_2__width_1 and_sz (
.din0 (tlb_tte_data[`DATA_VA_21_16_V]),
.din1 (tte_data_va_27_22_v_),
////////////////////////////////////////////////////////////////////////////
// tte_tag context muxing
// First level of muxing is done in lsu_tld_dp and comes in as tld_tag_c0
lsu_tgd_dp_mux_macro__mux_aope__ports_3__stack_14l__width_13 mx_tag_c0 (
.din0 (tld_tag_c0[12:0]),
.din1 (dcs_context1_e[12:0]),
.din2 (dcs_context0_e[12:0]),
.sel1 (tlc_sel_demap_tag_c1),
lsu_tgd_dp_buff_macro__stack_14l__width_13 buf_tag_c0 (
lsu_tgd_dp_mux_macro__mux_aope__ports_3__stack_14r__width_13 mx_tag_c1 (
.din0 (tld_tag_c1[12:0]),
.din1 (dcs_context0_e[12:0]),
.din2 (dcs_context1_e[12:0]),
.sel1 (tlc_sel_demap_tag_c0),
lsu_tgd_dp_buff_macro__stack_14r__width_13 buf_tag_c1 (
// Data access read format (sun4v TTE) is
// V NFO PRTY 0 0 PA IE E CP 0 P 0 W 0 SZ
// 63 | 62 | 61 | 60:56 | 55:40 | 39:13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5:3 | 2:0
// Tag read register format is
// PID R P U 0 VA Context
// 63:61 | 60 | 59 | 58 | 57:48 | 47:13 | 12:0
// Mux the different ASI read sources that are on the right side of the LSU
lsu_tgd_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 mx_asi_b (
.din0 ({32'd0,tgd_diag_tag_b[31:0]}),
.din1 ({tlb_tte_tag[`TAG_V], // V
tlb_tte_data[`DATA_NFO], // NFO
tlb_tte_data[`DATA_PARITY], // PARITY
tlb_tte_data[`DATA_PA_39_28_HI:`DATA_PA_39_28_LO], // PA
tlb_tte_data[`DATA_PA_27_22_HI:`DATA_PA_27_22_LO],
tlb_tte_data[`DATA_PA_21_16_HI:`DATA_PA_21_16_LO],
tlb_tte_data[`DATA_PA_15_13_HI:`DATA_PA_15_13_LO],
tlb_tte_data[`DATA_IE], // IE
tlb_tte_data[`DATA_E], // E
tlb_tte_data[`DATA_CP], // CP
tlb_tte_data[`DATA_P], // P
tlb_tte_data[`DATA_W], // W
tlb_tte_data[`DATA_VA_27_22_V], // SZ
tte_data_sz_1,tlb_tte_data[`DATA_VA_15_13_V] // SZ
.din2 ({tlb_tte_tag[`TAG_PID_HI:`TAG_PID_LO], // PID
tlb_tte_tag[`TAG_REAL], // REAL
tlb_tte_data[`TAG_PARITY], // PARITY
tlb_tte_tag[`TAG_VA_47_28_HI:`TAG_VA_27_22_LO],
tlb_tte_tag[`TAG_VA_21_16_HI:`TAG_VA_21_16_LO],
tlb_tte_tag[`TAG_VA_15_13_HI:`TAG_VA_15_13_LO],
tlb_tte_tag[`TAG_CNTX0_HI:`TAG_CNTX0_LO] // context
.din3 ({tlb_tte_tag[`TAG_PID_HI:`TAG_PID_LO], // PID
tlb_tte_tag[`TAG_REAL], // REAL
tlb_tte_data[`TAG_PARITY], // PARITY
tlb_tte_tag[`TAG_VA_47_28_HI:`TAG_VA_27_22_LO],
tlb_tte_tag[`TAG_VA_21_16_HI:`TAG_VA_21_16_LO],
tlb_tte_tag[`TAG_VA_15_13_HI:`TAG_VA_15_13_LO],
tlb_tte_tag[`TAG_CNTX1_HI:`TAG_CNTX1_LO] // context
.sel0 (dcc_rd_dt_diag_b),
.sel1 (dcc_tlb_data_read_b),
.sel2 (dcc_tlb_tag0_read_b),
.sel3 (dcc_tlb_tag1_read_b),
.dout (ldxa_asi_data_b[63:0])
lsu_tgd_dp_buff_macro__rep_1__stack_64c__width_64 buf_asi_b (
.din (ldxa_asi_data_b[63:0]),
.dout (tgd_ldxa_asi_data_b[63:0])
lsu_tgd_dp_buff_macro__left_19__minbuff_1__stack_64c__width_45 va_minbuf (
lsu_tgd_dp_msff_macro__left_13__stack_64c__width_51 dff_va_b (
.scan_in(dff_va_b_scanin),
.scan_out(dff_va_b_scanout),
tld_prty_256m ,tld_prty_4m ,tld_prty_64k ,tld_prty_8k ,tld_prty_ctxt0 ,tld_prty_ctxt1}),
tgd_prty_256m_b,tgd_prty_4m_b,tgd_prty_64k_b,tgd_prty_8k_b,tgd_prty_ctxt0_b,tgd_prty_ctxt1_b}),
///////////////////////////////////////////////////////////////
// Watchpoint mux and compare is here so it's close to the TLB
lsu_tgd_dp_msff_macro__left_19__stack_64c__width_45 dff_wpt_b (
.scan_in(dff_wpt_b_scanin),
.scan_out(dff_wpt_b_scanout),
.din (dcs_watchpoint_m[47:3]),
.dout (watchpoint_b[47:3]),
lsu_tgd_dp_cmp_macro__width_32 cmp_va_47_16 (
.din0 (watchpoint_b[47:16]),
lsu_tgd_dp_cmp_macro__width_16 cmp_va_15_3 (
.din0 ({3'b0,watchpoint_b[15:3]}),
.din1 ({3'b0,va_b[15:3]}),
lsu_tgd_dp_cmp_macro__width_32 cmp_pa_39_16 (
.din0 ({8'b0,watchpoint_b[39:16]}),
.din1 ({8'b0,tlb_pgnum[39:16]}),
lsu_tgd_dp_cmp_macro__width_16 cmp_pa_15_3 (
.din0 ({3'b0,watchpoint_b[15:3]}),
.din1 ({3'b0,tlb_pgnum[15:13],va_b[12:3]}),
lsu_tgd_dp_buff_macro__width_4 wpt_buf (
.din ({ va_wp_47_16, pa_wp_39_16, va_wp_15_3, pa_wp_15_3}),
.dout ({tgd_va_wp_47_16,tgd_pa_wp_39_16,tgd_va_wp_15_3,tgd_pa_wp_15_3})
lsu_tgd_dp_buff_macro__rep_1__width_10 tte_buf (
.din ({tlb_tte_data[`TAG_PARITY],tlb_tte_data[`DATA_VA_27_22_V],
tlb_tte_data[`DATA_VA_21_16_V],tlb_tte_data[`DATA_VA_15_13_V],
tlb_tte_data[`DATA_NFO:`DATA_W]}),
.dout ({tlb_tag_parity, tlb_pgsize[2:0],tlb_tte_nfo_b,tlb_tte_ie_b,
tlb_tte_cp_b,tlb_tte_ebit_b,tlb_tte_pbit_b,tlb_tte_wbit_b})
// BIST mux and tag comparator
lsu_tgd_dp_mux_macro__mux_aope__ports_3__stack_64c__width_64 bist_mx (
.din0 ({{4{bist_cmp_data[7:0]}},bist_cmp_data[7:6],tgd_diag_tag_b[31:2]}),
.din1 ({bist_cmp_data[7:1],tlb_tte_u_bit,bist_cmp_data[7:5],tlb_tte_tag[52:50],
bist_cmp_data[1],tlb_tte_tag[48:0]}),
.din2 ({tlb_tte_tag[65:53],bist_cmp_data[2:0],bist_cmp_data[7:0],
bist_cmp_data[7:6],tlb_tte_data[37:0]}),
.dout (bist_mux_data[63:0])
lsu_tgd_dp_cmp_macro__width_64 bist_cmp (
.din0 ({8{bist_cmp_data[7:0]}}),
.din1 (bist_mux_data[63:0]),
lsu_tgd_dp_cmp_macro__width_8 cambist_cmp (
.din0 ({1'b0,bist_cmp_data[6:0]}),
.din1 ({1'b0,tlb_tte_data[6:0]}),
.dout (lsu_mbi_tlb_data_cmp)
lsu_tgd_dp_buff_macro__width_5 cambist_buf (
.din ({tlb_cam_hit, tlb_context0_hit, tlb_cam_mhit,
tlb_tte_u_bit, tlb_tte_tag[`TAG_V]}),
.dout ({lsu_mbi_tlb_cam_hit,lsu_mbi_tlb_ctxt0_hit,lsu_mbi_tlb_cam_mhit,
lsu_mbi_tlb_used, lsu_mbi_tlb_valid})
assign dff_16b_prty_w01_scanin = scan_in ;
assign dff_16b_prty_w23_scanin = dff_16b_prty_w01_scanout ;
assign dff_diag_tag_scanin = dff_16b_prty_w23_scanout ;
assign dff_va_b_scanin = dff_diag_tag_scanout ;
assign dff_wpt_b_scanin = dff_va_b_scanout ;
assign scan_out = dff_wpt_b_scanout ;
module lsu_tgd_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
// parity macro (even parity)
module lsu_tgd_dp_prty_macro__width_16 (
// any PARAMS parms go into naming of macro
module lsu_tgd_dp_msff_macro__width_4 (
// xor macro for ports = 2,3
module lsu_tgd_dp_xor_macro__width_4 (
module lsu_tgd_dp_buff_macro__width_4 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_tgd_dp_mux_macro__mux_pgpe__ports_2__stack_32c__width_32 (
// any PARAMS parms go into naming of macro
module lsu_tgd_dp_msff_macro__mux_pgpe__ports_2__stack_32l__width_32 (
.so({so[30:0],scan_out}),
module lsu_tgd_dp_buff_macro__left_2__rep_1__stack_32c__width_29 (
module lsu_tgd_dp_inv_macro__width_1 (
// and macro for ports = 2,3,4
module lsu_tgd_dp_and_macro__ports_2__width_1 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_tgd_dp_mux_macro__mux_aope__ports_3__stack_14l__width_13 (
module lsu_tgd_dp_buff_macro__stack_14l__width_13 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_tgd_dp_mux_macro__mux_aope__ports_3__stack_14r__width_13 (
module lsu_tgd_dp_buff_macro__stack_14r__width_13 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_tgd_dp_mux_macro__mux_aonpe__ports_4__stack_64c__width_64 (
cl_dp1_muxbuff4_8x c0_0 (
module lsu_tgd_dp_buff_macro__rep_1__stack_64c__width_64 (
module lsu_tgd_dp_buff_macro__left_19__minbuff_1__stack_64c__width_45 (
// any PARAMS parms go into naming of macro
module lsu_tgd_dp_msff_macro__left_13__stack_64c__width_51 (
.so({so[49:0],scan_out}),
// any PARAMS parms go into naming of macro
module lsu_tgd_dp_msff_macro__left_19__stack_64c__width_45 (
.so({so[43:0],scan_out}),
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module lsu_tgd_dp_cmp_macro__width_32 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module lsu_tgd_dp_cmp_macro__width_16 (
module lsu_tgd_dp_buff_macro__rep_1__width_10 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module lsu_tgd_dp_mux_macro__mux_aope__ports_3__stack_64c__width_64 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module lsu_tgd_dp_cmp_macro__width_64 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module lsu_tgd_dp_cmp_macro__width_8 (
module lsu_tgd_dp_buff_macro__width_5 (