// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: mmu_asi_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// ========== Copyright Header End ============================================
wire stg1_en_lat_scanout;
wire stg2_en_lat_scanout;
wire stg3_en_lat_scanout;
wire stg4_en_lat_scanout;
wire mbist_run_lat_scanin;
wire mbist_run_lat_scanout;
wire mra0_wr_en_lat_scanin;
wire mra0_wr_en_lat_scanout;
wire mra1_wr_en_lat_scanin;
wire mra1_wr_en_lat_scanout;
wire scp0_wr_en_lat_scanin;
wire scp0_wr_en_lat_scanout;
wire scp1_wr_en_lat_scanin;
wire scp1_wr_en_lat_scanout;
wire mbist_addr_lat_scanin;
wire mbist_addr_lat_scanout;
wire mbist_wdata_lat_scanin;
wire mbist_wdata_lat_scanout;
wire mra0_rd_en_lat_scanin;
wire mra0_rd_en_lat_scanout;
wire mra1_rd_en_lat_scanin;
wire mra1_rd_en_lat_scanout;
wire scp0_rd_en_lat_scanin;
wire scp0_rd_en_lat_scanout;
wire scp1_rd_en_lat_scanin;
wire scp1_rd_en_lat_scanout;
wire mbist_cmpsel_lat_scanin;
wire mbist_cmpsel_lat_scanout;
wire [63:0] mbist_wr_data;
wire [7:0] mbist_wdata_2;
wire mra0_wr_en_2_lat_scanin;
wire mra0_wr_en_2_lat_scanout;
wire mra1_wr_en_2_lat_scanin;
wire mra1_wr_en_2_lat_scanout;
wire mra0_rd_en_2_lat_scanin;
wire mra0_rd_en_2_lat_scanout;
wire mra1_rd_en_2_lat_scanin;
wire mra1_rd_en_2_lat_scanout;
wire scp0_rd_en_2_lat_scanin;
wire scp0_rd_en_2_lat_scanout;
wire scp1_rd_en_2_lat_scanin;
wire scp1_rd_en_2_lat_scanout;
wire mbist_addr_2_lat_scanin;
wire mbist_addr_2_lat_scanout;
wire mbist_cmpsel_2_lat_scanin;
wire mbist_cmpsel_2_lat_scanout;
wire [1:0] mbist_cmpsel_2;
wire mbist_compare_data_lat_scanin;
wire mbist_compare_data_lat_scanout;
wire [7:0] compare_data_in;
wire [7:0] mbist_wdata_3;
wire mra0_rd_en_3_lat_scanin;
wire mra0_rd_en_3_lat_scanout;
wire mra1_rd_en_3_lat_scanin;
wire mra1_rd_en_3_lat_scanout;
wire scp0_rd_en_3_lat_scanin;
wire scp0_rd_en_3_lat_scanout;
wire scp1_rd_en_3_lat_scanin;
wire scp1_rd_en_3_lat_scanout;
wire mra0_rd_en_4_lat_scanin;
wire mra0_rd_en_4_lat_scanout;
wire mra1_rd_en_4_lat_scanin;
wire mra1_rd_en_4_lat_scanout;
wire mra0_fail_lat_scanin;
wire mra0_fail_lat_scanout;
wire mra1_fail_lat_scanin;
wire mra1_fail_lat_scanout;
wire scp0_fail_lat_scanin;
wire scp0_fail_lat_scanout;
wire scp1_fail_lat_scanin;
wire scp1_fail_lat_scanout;
wire [1:0] hwtw_config_0_in;
wire [7:0] wr_hwtw_config_dec;
wire [1:0] hwtw_config_0;
wire [1:0] hwtw_config_1_in;
wire [1:0] hwtw_config_1;
wire [1:0] hwtw_config_2_in;
wire [1:0] hwtw_config_2;
wire [1:0] hwtw_config_3_in;
wire [1:0] hwtw_config_3;
wire [1:0] hwtw_config_4_in;
wire [1:0] hwtw_config_4;
wire [1:0] hwtw_config_5_in;
wire [1:0] hwtw_config_5;
wire [1:0] hwtw_config_6_in;
wire [1:0] hwtw_config_6;
wire [1:0] hwtw_config_7_in;
wire [1:0] hwtw_config_7;
wire hwtw_config_0_lat_wmr_scanin;
wire hwtw_config_0_lat_wmr_scanout;
wire hwtw_config_1_lat_wmr_scanin;
wire hwtw_config_1_lat_wmr_scanout;
wire hwtw_config_2_lat_wmr_scanin;
wire hwtw_config_2_lat_wmr_scanout;
wire hwtw_config_3_lat_wmr_scanin;
wire hwtw_config_3_lat_wmr_scanout;
wire hwtw_config_4_lat_wmr_scanin;
wire hwtw_config_4_lat_wmr_scanout;
wire hwtw_config_5_lat_wmr_scanin;
wire hwtw_config_5_lat_wmr_scanout;
wire hwtw_config_6_lat_wmr_scanin;
wire hwtw_config_6_lat_wmr_scanout;
wire hwtw_config_7_lat_wmr_scanin;
wire hwtw_config_7_lat_wmr_scanout;
wire [63:0] hwtw_config_muxed;
wire [7:0] rd_hwtw_config_dec;
wire rng_stg1_data_scanin;
wire rng_stg1_data_scanout;
wire legal_data_in_page_size;
wire wr_itlb_data_access_2;
wire wr_dtlb_data_access_2;
wire [7:0] clear_data_in_write_;
wire legal_tsb_cfg_page_size;
wire rd_itlb_data_access;
wire wr_itlb_data_access;
wire rd_dtlb_data_access;
wire wr_dtlb_data_access;
wire [1:0] rd_sca_data_en_2;
wire [1:0] rd_sca_ecc_en_2;
wire scp_ctl_lat_scanout;
wire rd_scratchpad_4_lat_scanin;
wire rd_scratchpad_4_lat_scanout;
wire [1:0] mra_addr_sel_rd;
wire [1:0] mra_addr_sel_hw_tw;
wire req_grant_lat_scanin;
wire req_grant_lat_scanout;
wire [4:0] mra_rd_addr_1;
wire [4:0] mra_rd_addr_0;
wire mra_addr_lat_scanin;
wire mra_addr_lat_scanout;
wire [1:0] mra_to_r3_in_in;
wire [1:0] pmra_to_r3_in;
wire mra_rd_en_lat_scanin;
wire mra_rd_en_lat_scanout;
wire [1:0] mra_rd_en_last;
wire [1:0] mra_wr_en_3_in;
wire mra_sel_tsb_cfg_0_2_2;
wire mra_sel_tsb_cfg_1_3_2;
wire mra_wr_en_lat_scanin;
wire mra_wr_en_lat_scanout;
wire mra_wr_en_4_lat_scanin;
wire mra_wr_en_4_lat_scanout;
wire [1:0] mra_wr_en_out;
wire mra_sel_tsb_cfg_0_2_1;
wire mra_sel_tsb_cfg_1_3_1;
wire mra_sel_real_range_1;
wire mra_sel_physical_offset_1;
wire mra_sel_lat_scanout;
wire mra_sel_real_range_2;
wire mra_sel_physical_offset_2;
wire mra_sel_tsb_cfg_0_2_3;
wire mra_sel_tsb_cfg_1_3_3;
wire mra_sel_real_range_3;
wire mra_sel_physical_offset_3;
wire [63:0] dtlb0_tte_tag;
wire [63:0] dtlb1_tte_tag;
wire [63:0] scp0_ecc_bus;
wire [63:0] scp1_ecc_bus;
wire [63:0] mbist_scp0_0;
wire [63:0] mbist_scp0_1;
wire [63:0] mbist_scp0_2;
wire [63:0] mbist_scp1_0;
wire [63:0] mbist_scp1_1;
wire [63:0] mbist_scp1_2;
wire [1:0] use_dtlb_window;
wire [63:0] rd_t_p_c_data;
wire [63:0] rd_t_p_s_data;
wire stg2_data_lat_scanin;
wire stg2_data_lat_scanout;
wire stg2_ctl_lat_scanin;
wire stg2_ctl_lat_scanout;
wire wr_immu_tag_access_2;
wire wr_dmmu_tag_access_2;
wire [7:0] a_wr_immu_tag_access;
wire [7:0] a_wr_itlb_data_in;
wire [7:0] a_wr_itlb_data_access;
wire [7:0] a_wr_immu_demap;
wire [7:0] a_wr_dmmu_tag_access;
wire [7:0] a_wr_dtlb_data_in;
wire [7:0] a_wr_dtlb_data_access;
wire [7:0] a_wr_dmmu_demap;
wire dae_req_lat_scanout;
wire check_ecc_lat_scanin;
wire check_ecc_lat_scanout;
wire [1:0] pmra_to_r4_in;
wire pmra_to_r4_lat_scanin;
wire pmra_to_r4_lat_scanout;
wire sca_index_lat_scanin;
wire sca_index_lat_scanout;
wire [64:0] rngf_cdbus_2;
wire [64:0] dtlb0_tte_data;
wire [64:0] dtlb1_tte_data;
wire [64:0] tsb_ptr_data;
wire stg3_ctl_lat_scanin;
wire stg3_ctl_lat_scanout;
wire asi_read_lat_scanin;
wire asi_read_lat_scanout;
wire dtlb_window_used_last;
wire idata_in_data_access;
wire ddata_in_data_access;
wire [7:0] wrote_dtlb_in;
wire sel_rd_dtte_hwtw_in;
wire [7:0] rd_dtte_hwtw_in;
wire idata_in_data_access_2_lat_scanin;
wire idata_in_data_access_2_lat_scanout;
wire idata_in_data_access_2;
wire [7:0] rd_itte_last_in;
wire [7:0] rd_itte_last_last_in;
wire [7:0] rd_itte_data_in;
wire [7:0] rd_itte_last_last;
wire [7:0] rd_itte_tag_in;
wire rd_itte_lat_scanout;
wire [7:0] prd_itte_last;
wire dtlb_window_used_last_lat_scanin;
wire dtlb_window_used_last_lat_scanout;
wire wrote_dtlb_tg1_lat_scanin;
wire wrote_dtlb_tg1_lat_scanout;
wire wrote_dtlb_tg0_lat_scanin;
wire wrote_dtlb_tg0_lat_scanout;
wire [7:0] reload_done_in;
wire reload_done_tg1_lat_scanin;
wire reload_done_tg1_lat_scanout;
wire reload_done_tg0_lat_scanin;
wire reload_done_tg0_lat_scanout;
wire dtlb_reload_stall_in;
wire dtlb_reload_stall_lat_scanin;
wire dtlb_reload_stall_lat_scanout;
wire dtlb_reload_lat_scanin;
wire dtlb_reload_lat_scanout;
wire [3:0] wr_tsb_cfg_enc;
wire wr_tsb_cfg_lat_scanin;
wire wr_tsb_cfg_lat_scanout;
wire [3:0] wr_tsb_cfg_enc_2;
wire [3:0] wr_tsb_cfg_enc_3;
wire [3:0] wr_tsb_cfg_enc_4;
wire hw_tw_e_lat_wmr_scanin;
wire hw_tw_e_lat_wmr_scanout;
wire tsb_hwtw_en_lat_scanin;
wire tsb_hwtw_en_lat_scanout;
wire htc_mra_addr_lat_scanin;
wire htc_mra_addr_lat_scanout;
wire [7:0] htc_enables_1_2;
wire [7:0] htc_enables_0_2;
wire [3:0] htc_sel_tsb_cfg;
wire [1:0] htc_hwtw_en_1_2;
wire [1:0] htc_hwtw_en_0_2;
wire data_access_index_lat_scanin;
wire data_access_index_lat_scanout;
wire error_inject_lat_scanin;
wire error_inject_lat_scanout;
wire tag_access_tid_0_lat_scanin;
wire tag_access_tid_0_lat_scanout;
wire [1:0] tag_access_tid_0;
wire i_tag_access_0_lat_scanin;
wire i_tag_access_0_lat_scanout;
wire d_tag_access_0_lat_scanin;
wire d_tag_access_0_lat_scanout;
wire tag_access_tid_1_lat_scanin;
wire tag_access_tid_1_lat_scanout;
wire [1:0] tag_access_tid_1;
wire i_tag_access_1_lat_scanin;
wire i_tag_access_1_lat_scanout;
wire d_tag_access_1_lat_scanin;
wire d_tag_access_1_lat_scanout;
wire [7:0] i_tag_access_exc;
wire [7:0] d_tag_access_exc;
input spc_aclk_wmr; // Warm reset (non)scan
input [7:0] htc_itlb_clken;
input [7:0] htc_dtlb_clken;
input [1:0] tlu_tag_access_tid_0_b; // Tag access power management
input tlu_i_tag_access_0_b; // Tag access power management
input tlu_d_tag_access_0_b; // Tag access power management
input [1:0] tlu_tag_access_tid_1_b; // Tag access power management
input tlu_i_tag_access_1_b; // Tag access power management
input tlu_d_tag_access_1_b; // Tag access power management
input mbi_mra0_write_en; // MBIST write control
input mbi_mra1_write_en; // MBIST write control
input mbi_scp0_write_en; // MBIST write control
input mbi_scp1_write_en; // MBIST write control
input [4:0] mbi_addr; // 32 entry addressability for MBIST
input mbi_run; // Select MBIST controls
input [7:0] mbi_wdata; // MBIST write data
input mbi_mra0_read_en; // MBIST read control
input mbi_mra1_read_en; // MBIST read control
input mbi_scp0_read_en; // MBIST read control
input mbi_scp1_read_en; // MBIST read control
input [1:0] mbi_mmu_cmpsel; // Mux (DEC) between 32 bit chunks
input mbd_compare; // MBIST compare result
input error_inject_enable;
input [7:0] error_inject_mask;
input [64:0] lsu_rngf_cdbus; // control/data bus from lsu
input [7:0] tlu_iht_request; // ITLB hardware tablewalk request
input [7:0] tlu_dht_request; // DTLB hardware tablewalk request
input [7:0] tlu_release_tte; // TTE write has been transmitted
input [7:0] tlu_ceter_pscce;
input sel_scac; // Correctable error on scratchpad
input sel_scau; // Uncorrectable error on scratchpad
input [63:0] ase_mra_rd_data;
input [63:0] asd0_asi_rd_data;
input [63:0] asd1_asi_rd_data;
input [47:0] asd0_dtte_tag;
input [47:0] asd1_dtte_tag;
input [54:0] asd0_dtte_data;
input [54:0] asd1_dtte_data;
input [6:0] asd0_itte_index; // Flop and send to IFU
input [6:0] asd1_itte_index; // Flop and send to IFU
input asd0_asi_zero_context;
input asd1_asi_zero_context;
input [4:0] htc_mra_addr_in;
input [1:0] htc_mra_rd_en;
input [7:0] htc_wr_itlb_data_in;
input [7:0] htc_wr_dtlb_data_in;
input [7:0] mmu_i_unauth_access;
input [7:0] mmu_i_tsb_miss;
input [7:0] mmu_d_tsb_miss;
input [7:0] mmu_i_tte_outofrange;
input [7:0] mmu_d_tte_outofrange;
input [7:0] mmu_i_eccerr; // HW TW had MRA or L2 error on I rld
input [7:0] mmu_d_eccerr; // HW TW had MRA or L2 error on D rld
output [7:0] asi_error_mask;
output [4:0] asi_scp_addr;
output [1:0] asi_scp_wr_en;
output [1:0] asi_scp_rd_en;
output [4:0] asi_mra_rd_addr_0; // For reads (flops now in array)
output [4:0] asi_mra_rd_addr_1; // For reads (flops now in array)
output [1:0] asi_mra_rd_en; // (flops now in array)
output [4:0] asi_mra_wr_addr;
output [1:0] asi_mra_wr_en;
output [1:0] asi_mra_rd_en_last; // to capture read data for rd-modify-wr
output asi_rd_tsb_cfg_0_2;
output asi_rd_tsb_cfg_1_3;
output asi_rd_real_range;
output asi_rd_physical_offset;
output asi_sel_mra_0_in; // Active in cycle 2
output asi_mra_wr_en_next; // Power management for rd-mod-wr flops
output [7:0] asi_rd_immu_tag_target;
output [7:0] asi_rd_immu_tag_access;
output [7:0] asi_rd_dmmu_tag_target;
output [7:0] asi_rd_dmmu_tag_access;
output [1:0] asi_rd_i_access_target;
output [1:0] asi_rd_d_access_target;
output [1:0] asi_rd_access_target;
output [7:0] asi_rd_itte_tag;
output [7:0] asi_rd_itte_data;
output [6:0] asi_rd_dtte;
output [7:0] asi_wr_immu_tag_access;
output [7:0] asi_wr_itlb_data_in;
output [7:0] asi_wr_itlb_data_access;
output [7:0] asi_wr_immu_demap;
output [7:0] asi_wr_immu_demap_p;
output [7:0] asi_wr_immu_demap_n;
output [7:0] asi_wr_dmmu_tag_access;
output [7:0] asi_wr_dtlb_data_in;
output [7:0] asi_wr_dtlb_data_access;
output [7:0] asi_wr_partition_id;
output [7:0] asi_wr_dmmu_demap;
output [7:0] asi_wr_dmmu_demap_p;
output [7:0] asi_wr_dmmu_demap_s_n;
output [7:0] asi_wr_p_context_0;
output [1:0] asi_p_context_0_en;
output [2:0] asi_tag_access_sel;
output asi_tsb_ptr_req_valid;
output [2:0] asi_tsb_ptr_req; // HW TW: which thread gets tag access
output [1:0] asi_tsb_ptr_number; // HW TW: which config reg to use
output [1:0] asi_tsb_hwtw_enable_0; // TSB_CFG[63]; same timing as MRA output
output [1:0] asi_tsb_hwtw_enable_1; // TSB_CFG[63]; same timing as MRA output
output [63:0] asi_seg_wr_data;
output [63:0] asi_wr_data;
output [63:0] asi_mra_wr_data;
output asi_mra_req_grant; // Hardware tablewalk request granted
output [63:0] asi_rd_data;
output [1:0] asi_hwtw_config_0;
output [1:0] asi_hwtw_config_1;
output [1:0] asi_hwtw_config_2;
output [1:0] asi_hwtw_config_3;
output [1:0] asi_hwtw_config_4;
output [1:0] asi_hwtw_config_5;
output [1:0] asi_hwtw_config_6;
output [1:0] asi_hwtw_config_7;
output asi_sel_en; // Clock enable for scratchpad ECC check
output [7:0] asi_i_tag_access_en;
output [7:0] asi_d_tag_access_en;
output [7:0] asi_i_data_in_en;
output [7:0] asi_d_data_in_en;
output [7:0] asi_mbist_wdata; // MBIST
output [7:0] asi_ase_compare_data; // MBIST
output [7:0] asi_compare_data; // MBIST
output [31:0] asi_mbd_scp_data; // MBIST
output asi_mbd_sel_scp; // MBIST
output [7:0] asi_mbist_ecc_in; // MBIST
output [3:2] asi_mbist_ecc; // MBIST
output asi_mbist_run; // MBIST
output asi_ecc_cmpsel_in; // MBIST
output [1:0] asi_ase_cmpsel_in; // MBIST
output [64:0] mmu_asi_data; // ASI read data for fast bus (to TLU)
output mmu_asi_read; // Valid for MMU ASI read
output [7:0] mmu_write_itlb;
output mmu_dtlb_reload_stall;
output [7:0] mmu_hw_tw_enable;
output mmu_asi_cecc; // Correctable ECC error on ASI read
output mmu_asi_uecc; // Uncorrectable ECC error on ASI read
output [2:0] mmu_asi_tid; // Thread for reported error
output [2:0] mmu_asi_index; // Index of the failure (rest is TID)
output mmu_asi_mra_not_sca; // 1: MRA error 0: Scratchpad error
output mmu_dae_req; // data_access_exception for bad pg size
output [2:0] mmu_dae_tid;
output [7:0] mmu_reload_done;
output [6:0] mmu_index; // Index and valid from idata_access
output mmu_mbi_mra0_fail; // MBIST
output mmu_mbi_mra1_fail; // MBIST
output mmu_mbi_scp0_fail; // MBIST
output mmu_mbi_scp1_fail; // MBIST
//////////////////////////////////////////////////////////////////////
assign pce_ov = tcu_pce_ov;
mmu_asi_ctl_l1clkhdr_ctl_macro free_clken (
//////////////////////////////////////////////////////////////////////////////
mmu_asi_ctl_msff_ctl_macro__width_1 stg1_en_lat (
.scan_in(stg1_en_lat_scanin),
.scan_out(stg1_en_lat_scanout),
(lsu_rngf_cdbus[64] & lsu_rngf_cdbus[63]) |
(~lsu_rngf_cdbus[64] & stg2_en) |
mmu_asi_ctl_msff_ctl_macro__width_1 stg2_en_lat (
.scan_in(stg2_en_lat_scanin),
.scan_out(stg2_en_lat_scanout),
| {pstg2_en, prd_itte[7:0], prd_dtte[7:0], rd_dtte_hwtw[7:0]};
mmu_asi_ctl_msff_ctl_macro__width_1 stg3_en_lat (
.scan_in(stg3_en_lat_scanin),
.scan_out(stg3_en_lat_scanout),
mmu_asi_ctl_msff_ctl_macro__width_1 stg4_en_lat (
.scan_in(stg4_en_lat_scanin),
.scan_out(stg4_en_lat_scanout),
stg1_en | stg2_en | stg3_en | stg4_en;
mmu_asi_ctl_l1clkhdr_ctl_macro stg1_4_clken (
mbist_run | ~lsu_mmu_pmen;
mmu_asi_ctl_l1clkhdr_ctl_macro mbist_clken (
//////////////////////////////////////////////////////////////////////////////
// Note: mbist_run is used to control power management,
// so do not power manage this flop
mmu_asi_ctl_msff_ctl_macro__width_1 mbist_run_lat (
.scan_in(mbist_run_lat_scanin),
.scan_out(mbist_run_lat_scanout),
mmu_asi_ctl_msff_ctl_macro__width_1 mra0_wr_en_lat (
.scan_in(mra0_wr_en_lat_scanin),
.scan_out(mra0_wr_en_lat_scanout),
.din (mbi_mra0_write_en ),
.dout (mbist_mra0_wr_en ),
mmu_asi_ctl_msff_ctl_macro__width_1 mra1_wr_en_lat (
.scan_in(mra1_wr_en_lat_scanin),
.scan_out(mra1_wr_en_lat_scanout),
.din (mbi_mra1_write_en ),
.dout (mbist_mra1_wr_en ),
mmu_asi_ctl_msff_ctl_macro__width_1 scp0_wr_en_lat (
.scan_in(scp0_wr_en_lat_scanin),
.scan_out(scp0_wr_en_lat_scanout),
.din (mbi_scp0_write_en ),
.dout (mbist_scp0_wr_en ),
mmu_asi_ctl_msff_ctl_macro__width_1 scp1_wr_en_lat (
.scan_in(scp1_wr_en_lat_scanin),
.scan_out(scp1_wr_en_lat_scanout),
.din (mbi_scp1_write_en ),
.dout (mbist_scp1_wr_en ),
mmu_asi_ctl_msff_ctl_macro__width_5 mbist_addr_lat (
.scan_in(mbist_addr_lat_scanin),
.scan_out(mbist_addr_lat_scanout),
.dout (mbist_addr [4:0] ),
mmu_asi_ctl_msff_ctl_macro__width_8 mbist_wdata_lat (
.scan_in(mbist_wdata_lat_scanin),
.scan_out(mbist_wdata_lat_scanout),
.dout (mbist_wdata [7:0] ),
mmu_asi_ctl_msff_ctl_macro__width_1 mra0_rd_en_lat (
.scan_in(mra0_rd_en_lat_scanin),
.scan_out(mra0_rd_en_lat_scanout),
.din (mbi_mra0_read_en ),
.dout (mbist_mra0_rd_en ),
mmu_asi_ctl_msff_ctl_macro__width_1 mra1_rd_en_lat (
.scan_in(mra1_rd_en_lat_scanin),
.scan_out(mra1_rd_en_lat_scanout),
.din (mbi_mra1_read_en ),
.dout (mbist_mra1_rd_en ),
mmu_asi_ctl_msff_ctl_macro__width_1 scp0_rd_en_lat (
.scan_in(scp0_rd_en_lat_scanin),
.scan_out(scp0_rd_en_lat_scanout),
.din (mbi_scp0_read_en ),
.dout (mbist_scp0_rd_en ),
mmu_asi_ctl_msff_ctl_macro__width_1 scp1_rd_en_lat (
.scan_in(scp1_rd_en_lat_scanin),
.scan_out(scp1_rd_en_lat_scanout),
.din (mbi_scp1_read_en ),
.dout (mbist_scp1_rd_en ),
mmu_asi_ctl_msff_ctl_macro__width_2 mbist_cmpsel_lat (
.scan_in(mbist_cmpsel_lat_scanin),
.scan_out(mbist_cmpsel_lat_scanout),
.din (mbi_mmu_cmpsel [1:0] ),
.dout (mbist_cmpsel [1:0] ),
assign mbist_wr_data[63:0] =
assign asi_mbist_wdata[7:0] =
assign asi_mbist_ecc_in[7:0] =
mbist_wdata[7:0] & {8 {mbist_run}};
assign asi_mbist_ecc[3:2] =
mbist_wdata_2[3:2] & {2 {mbist_run}};
mmu_asi_ctl_msff_ctl_macro__width_1 mra0_wr_en_2_lat (
.scan_in(mra0_wr_en_2_lat_scanin),
.scan_out(mra0_wr_en_2_lat_scanout),
.din (mbist_mra0_wr_en ),
.dout (mbist_mra0_wr_en_2 ),
mmu_asi_ctl_msff_ctl_macro__width_1 mra1_wr_en_2_lat (
.scan_in(mra1_wr_en_2_lat_scanin),
.scan_out(mra1_wr_en_2_lat_scanout),
.din (mbist_mra1_wr_en ),
.dout (mbist_mra1_wr_en_2 ),
mmu_asi_ctl_msff_ctl_macro__width_1 mra0_rd_en_2_lat (
.scan_in(mra0_rd_en_2_lat_scanin),
.scan_out(mra0_rd_en_2_lat_scanout),
.din (mbist_mra0_rd_en ),
.dout (mbist_mra0_rd_en_2 ),
mmu_asi_ctl_msff_ctl_macro__width_1 mra1_rd_en_2_lat (
.scan_in(mra1_rd_en_2_lat_scanin),
.scan_out(mra1_rd_en_2_lat_scanout),
.din (mbist_mra1_rd_en ),
.dout (mbist_mra1_rd_en_2 ),
mmu_asi_ctl_msff_ctl_macro__width_1 scp0_rd_en_2_lat (
.scan_in(scp0_rd_en_2_lat_scanin),
.scan_out(scp0_rd_en_2_lat_scanout),
.din (mbist_scp0_rd_en ),
.dout (mbist_scp0_rd_en_2 ),
mmu_asi_ctl_msff_ctl_macro__width_1 scp1_rd_en_2_lat (
.scan_in(scp1_rd_en_2_lat_scanin),
.scan_out(scp1_rd_en_2_lat_scanout),
.din (mbist_scp1_rd_en ),
.dout (mbist_scp1_rd_en_2 ),
mmu_asi_ctl_msff_ctl_macro__width_5 mbist_addr_2_lat (
.scan_in(mbist_addr_2_lat_scanin),
.scan_out(mbist_addr_2_lat_scanout),
.din (mbist_addr [4:0] ),
.dout (mbist_addr_2 [4:0] ),
mmu_asi_ctl_msff_ctl_macro__width_2 mbist_cmpsel_2_lat (
.scan_in(mbist_cmpsel_2_lat_scanin),
.scan_out(mbist_cmpsel_2_lat_scanout),
.din (mbist_cmpsel [1:0] ),
.dout (mbist_cmpsel_2 [1:0] ),
mmu_asi_ctl_msff_ctl_macro__width_24 mbist_compare_data_lat (
.scan_in(mbist_compare_data_lat_scanin),
.scan_out(mbist_compare_data_lat_scanout),
.din ({mbist_wdata [7:0],
.dout ({mbist_wdata_2 [7:0],
assign mbist_mra_rd_en_3 =
mbist_mra0_rd_en_3 | mbist_mra1_rd_en_3;
assign compare_data_in[7:0] =
(mbist_wdata_2[7:0] & {8 {~mbist_mra_rd_en_3}}) |
(mbist_wdata_3[7:0] & {8 { mbist_mra_rd_en_3}}) ;
assign asi_ase_compare_data[7:0] =
assign asi_compare_data[7:0] =
assign mbist_scp0_0_rd_en =
mbist_scp0_rd_en_2 & (mbist_cmpsel_2[1:0] == 2'b00);
assign mbist_scp0_1_rd_en =
mbist_scp0_rd_en_2 & (mbist_cmpsel_2[1:0] == 2'b01);
assign mbist_scp0_2_rd_en =
mbist_scp0_rd_en_2 & (mbist_cmpsel_2[1:0] == 2'b10);
assign mbist_scp1_0_rd_en =
mbist_scp1_rd_en_2 & (mbist_cmpsel_2[1:0] == 2'b00);
assign mbist_scp1_1_rd_en =
mbist_scp1_rd_en_2 & (mbist_cmpsel_2[1:0] == 2'b01);
assign mbist_scp1_2_rd_en =
mbist_scp1_rd_en_2 & (mbist_cmpsel_2[1:0] == 2'b10);
assign asi_ase_cmpsel_in[1:0] =
mmu_asi_ctl_msff_ctl_macro__width_1 mra0_rd_en_3_lat (
.scan_in(mra0_rd_en_3_lat_scanin),
.scan_out(mra0_rd_en_3_lat_scanout),
.din (mbist_mra0_rd_en_2 ),
.dout (mbist_mra0_rd_en_3 ),
mmu_asi_ctl_msff_ctl_macro__width_1 mra1_rd_en_3_lat (
.scan_in(mra1_rd_en_3_lat_scanin),
.scan_out(mra1_rd_en_3_lat_scanout),
.din (mbist_mra1_rd_en_2 ),
.dout (mbist_mra1_rd_en_3 ),
mmu_asi_ctl_msff_ctl_macro__width_1 scp0_rd_en_3_lat (
.scan_in(scp0_rd_en_3_lat_scanin),
.scan_out(scp0_rd_en_3_lat_scanout),
.din (mbist_scp0_rd_en_2 ),
.dout (mbist_scp0_rd_en_3 ),
mmu_asi_ctl_msff_ctl_macro__width_1 scp1_rd_en_3_lat (
.scan_in(scp1_rd_en_3_lat_scanin),
.scan_out(scp1_rd_en_3_lat_scanout),
.din (mbist_scp1_rd_en_2 ),
.dout (mbist_scp1_rd_en_3 ),
mbist_scp0_rd_en_3 | mbist_scp1_rd_en_3;
mmu_asi_ctl_msff_ctl_macro__width_1 mra0_rd_en_4_lat (
.scan_in(mra0_rd_en_4_lat_scanin),
.scan_out(mra0_rd_en_4_lat_scanout),
.din (mbist_mra0_rd_en_3 ),
.dout (mbist_mra0_rd_en_4 ),
mmu_asi_ctl_msff_ctl_macro__width_1 mra1_rd_en_4_lat (
.scan_in(mra1_rd_en_4_lat_scanin),
.scan_out(mra1_rd_en_4_lat_scanout),
.din (mbist_mra1_rd_en_3 ),
.dout (mbist_mra1_rd_en_4 ),
~mbd_compare & mbist_mra0_rd_en_4;
~mbd_compare & mbist_mra1_rd_en_4;
~mbd_compare & mbist_scp0_rd_en_3;
~mbd_compare & mbist_scp1_rd_en_3;
// Generate select for MRA ECC muxing for MBIST
assign asi_ecc_cmpsel_in =
mmu_asi_ctl_msff_ctl_macro__width_1 mra0_fail_lat (
.scan_in(mra0_fail_lat_scanin),
.scan_out(mra0_fail_lat_scanout),
mmu_asi_ctl_msff_ctl_macro__width_1 mra1_fail_lat (
.scan_in(mra1_fail_lat_scanin),
.scan_out(mra1_fail_lat_scanout),
mmu_asi_ctl_msff_ctl_macro__width_1 scp0_fail_lat (
.scan_in(scp0_fail_lat_scanin),
.scan_out(scp0_fail_lat_scanout),
mmu_asi_ctl_msff_ctl_macro__width_1 scp1_fail_lat (
.scan_in(scp1_fail_lat_scanin),
.scan_out(scp1_fail_lat_scanout),
assign mmu_mbi_mra0_fail =
assign mmu_mbi_mra1_fail =
assign mmu_mbi_scp0_fail =
assign mmu_mbi_scp1_fail =
//////////////////////////////////////////////////////////////////////////////
assign hwtw_config_0_in[1:0] =
({2 { wr_hwtw_config_dec[0]}} & data_1 [1:0]) |
({2 {~wr_hwtw_config_dec[0]}} & hwtw_config_0 [1:0]) ;
assign hwtw_config_1_in[1:0] =
({2 { wr_hwtw_config_dec[1]}} & data_1 [1:0]) |
({2 {~wr_hwtw_config_dec[1]}} & hwtw_config_1 [1:0]) ;
assign hwtw_config_2_in[1:0] =
({2 { wr_hwtw_config_dec[2]}} & data_1 [1:0]) |
({2 {~wr_hwtw_config_dec[2]}} & hwtw_config_2 [1:0]) ;
assign hwtw_config_3_in[1:0] =
({2 { wr_hwtw_config_dec[3]}} & data_1 [1:0]) |
({2 {~wr_hwtw_config_dec[3]}} & hwtw_config_3 [1:0]) ;
assign hwtw_config_4_in[1:0] =
({2 { wr_hwtw_config_dec[4]}} & data_1 [1:0]) |
({2 {~wr_hwtw_config_dec[4]}} & hwtw_config_4 [1:0]) ;
assign hwtw_config_5_in[1:0] =
({2 { wr_hwtw_config_dec[5]}} & data_1 [1:0]) |
({2 {~wr_hwtw_config_dec[5]}} & hwtw_config_5 [1:0]) ;
assign hwtw_config_6_in[1:0] =
({2 { wr_hwtw_config_dec[6]}} & data_1 [1:0]) |
({2 {~wr_hwtw_config_dec[6]}} & hwtw_config_6 [1:0]) ;
assign hwtw_config_7_in[1:0] =
({2 { wr_hwtw_config_dec[7]}} & data_1 [1:0]) |
({2 {~wr_hwtw_config_dec[7]}} & hwtw_config_7 [1:0]) ;
mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_0_lat ( // FS:wmr_protect
.scan_in(hwtw_config_0_lat_wmr_scanin),
.scan_out(hwtw_config_0_lat_wmr_scanout),
.din (hwtw_config_0_in [1:0] ),
.dout (hwtw_config_0 [1:0] ),
mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_1_lat ( // FS:wmr_protect
.scan_in(hwtw_config_1_lat_wmr_scanin),
.scan_out(hwtw_config_1_lat_wmr_scanout),
.din (hwtw_config_1_in [1:0] ),
.dout (hwtw_config_1 [1:0] ),
mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_2_lat ( // FS:wmr_protect
.scan_in(hwtw_config_2_lat_wmr_scanin),
.scan_out(hwtw_config_2_lat_wmr_scanout),
.din (hwtw_config_2_in [1:0] ),
.dout (hwtw_config_2 [1:0] ),
mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_3_lat ( // FS:wmr_protect
.scan_in(hwtw_config_3_lat_wmr_scanin),
.scan_out(hwtw_config_3_lat_wmr_scanout),
.din (hwtw_config_3_in [1:0] ),
.dout (hwtw_config_3 [1:0] ),
mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_4_lat ( // FS:wmr_protect
.scan_in(hwtw_config_4_lat_wmr_scanin),
.scan_out(hwtw_config_4_lat_wmr_scanout),
.din (hwtw_config_4_in [1:0] ),
.dout (hwtw_config_4 [1:0] ),
mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_5_lat ( // FS:wmr_protect
.scan_in(hwtw_config_5_lat_wmr_scanin),
.scan_out(hwtw_config_5_lat_wmr_scanout),
.din (hwtw_config_5_in [1:0] ),
.dout (hwtw_config_5 [1:0] ),
mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_6_lat ( // FS:wmr_protect
.scan_in(hwtw_config_6_lat_wmr_scanin),
.scan_out(hwtw_config_6_lat_wmr_scanout),
.din (hwtw_config_6_in [1:0] ),
.dout (hwtw_config_6 [1:0] ),
mmu_asi_ctl_msff_ctl_macro__width_2 hwtw_config_7_lat ( // FS:wmr_protect
.scan_in(hwtw_config_7_lat_wmr_scanin),
.scan_out(hwtw_config_7_lat_wmr_scanout),
.din (hwtw_config_7_in [1:0] ),
.dout (hwtw_config_7 [1:0] ),
assign asi_hwtw_config_0[1:0] =
assign asi_hwtw_config_1[1:0] =
assign asi_hwtw_config_2[1:0] =
assign asi_hwtw_config_3[1:0] =
assign asi_hwtw_config_4[1:0] =
assign asi_hwtw_config_5[1:0] =
assign asi_hwtw_config_6[1:0] =
assign asi_hwtw_config_7[1:0] =
assign hwtw_config_muxed[63:2] =
assign hwtw_config_muxed[1:0] =
({2 {rd_hwtw_config_dec[0]}} & hwtw_config_0[1:0]) |
({2 {rd_hwtw_config_dec[1]}} & hwtw_config_1[1:0]) |
({2 {rd_hwtw_config_dec[2]}} & hwtw_config_2[1:0]) |
({2 {rd_hwtw_config_dec[3]}} & hwtw_config_3[1:0]) |
({2 {rd_hwtw_config_dec[4]}} & hwtw_config_4[1:0]) |
({2 {rd_hwtw_config_dec[5]}} & hwtw_config_5[1:0]) |
({2 {rd_hwtw_config_dec[6]}} & hwtw_config_6[1:0]) |
({2 {rd_hwtw_config_dec[7]}} & hwtw_config_7[1:0]) ;
//////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
// Stage the packet coming on the ring
mmu_asi_ctl_msff_ctl_macro__width_64 rng_stg1_data (
.scan_in(rng_stg1_data_scanin),
.scan_out(rng_stg1_data_scanout),
.din (data_1_in [63:0] ),
// register control bit, bit 64 indicates whether ctl packet or data packet
mmu_asi_ctl_msff_ctl_macro__width_1 ctl_1_lat (
.scan_in(ctl_1_lat_scanin),
.scan_out(ctl_1_lat_scanout),
.din (lsu_rngf_cdbus [64 ] ),
ctl_1 & data_1[63] & ~data_1[62] & (data_1[61:60] == 2'b00);
// Scratchpad address is data_1[05:03] for regs 0 to 7
asi & ((data_1[55:48] == 8'h20) | (data_1[55:48] == 8'h4F)) ;
scratchpad & ~data_1[59];
// Context registers at 0x08, 0x10, 0x108, 0x110
asi & (data_1[55:48] == 8'h21);
context & ~data_1[8] & ~data_1[4] & data_1[3];
p_context_0 & ~data_1[59];
// IMMU tag target at 0x00, IMMU SFSR at 0x18, IMMU tag access at 0x30
// Note that ISFSR is in TLU, not MMU
asi & (data_1[55:48] == 8'h50);
asi_50 & data_1[59] & ~data_1[3];
asi_50 & (data_1[7:3] == 5'b00000);
assign rd_immu_tag_target =
immu_tag_target & data_1[59];
asi_50 & (data_1[7:3] == 5'b00110);
assign rd_immu_tag_access =
immu_tag_access & data_1[59];
assign wr_immu_tag_access =
immu_tag_access & ~data_1[59];
// Real range at 0x108, 110, 118, 120; physical offset at 0x208, 210, 218, 220
asi & (data_1[55:48] == 8'h52);
range_offset & data_1[59];
range_offset & (data_1[9:8] == 2'b01) & (data_1[5:3] == 3'b001);
range_offset & (data_1[9:8] == 2'b01) & (data_1[5:3] == 3'b010);
range_offset & (data_1[9:8] == 2'b01) & (data_1[5:3] == 3'b011);
range_offset & (data_1[9:8] == 2'b01) & (data_1[5:3] == 3'b100);
assign physical_offset_0 =
range_offset & (data_1[9:8] == 2'b10) & (data_1[5:3] == 3'b001);
assign physical_offset_1 =
range_offset & (data_1[9:8] == 2'b10) & (data_1[5:3] == 3'b010);
assign physical_offset_2 =
range_offset & (data_1[9:8] == 2'b10) & (data_1[5:3] == 3'b011);
assign physical_offset_3 =
range_offset & (data_1[9:8] == 2'b10) & (data_1[5:3] == 3'b100);
// ITLB data in reg at 0x00, TSB configurations at 0x[1-4][0,8],
// TSB pointers at 0x[5-8][0,8],
// tablewalk in progress registers at 0x90, 0x98
asi & (data_1[55:48] == 8'h54);
asi_54 & (data_1[7:3] == 5'b00000);
itlb_data_in & ~data_1[59];
asi_54 & (data_1[7:3] == 5'b00010);
asi_54 & (data_1[7:3] == 5'b00011);
asi_54 & (data_1[7:3] == 5'b00100);
asi_54 & (data_1[7:3] == 5'b00101);
asi_54 & (data_1[7:3] == 5'b00110);
asi_54 & (data_1[7:3] == 5'b00111);
asi_54 & (data_1[7:3] == 5'b01000);
asi_54 & (data_1[7:3] == 5'b01001);
z_tsb_cfg_0 & ~data_1[59];
z_tsb_cfg_1 & ~data_1[59];
z_tsb_cfg_2 & ~data_1[59];
z_tsb_cfg_3 & ~data_1[59];
nz_tsb_cfg_0 & ~data_1[59];
nz_tsb_cfg_1 & ~data_1[59];
nz_tsb_cfg_2 & ~data_1[59];
nz_tsb_cfg_3 & ~data_1[59];
asi_54 & (data_1[7:3] == 5'b01010);
asi_54 & (data_1[7:3] == 5'b01011);
asi_54 & (data_1[7:3] == 5'b01100);
asi_54 & (data_1[7:3] == 5'b01101);
asi_54 & (data_1[7:3] == 5'b01110);
asi_54 & (data_1[7:3] == 5'b01111);
asi_54 & (data_1[7:3] == 5'b10000);
asi_54 & (data_1[7:3] == 5'b10001);
ctl_2 & data_2[63] & ~data_2[62] & (data_2[61:60] == 2'b00);
asi_2 & (data_2[55:48] == 8'h54);
assign t_p_c_2 = // tablewalk_pending_control
asi_54_2 & (data_2[7:3] == 5'b10010);
assign t_p_s_2 = // tablewalk_pending_status
asi_54_2 & (data_2[7:3] == 5'b10011);
t_p_c_2 & data_2[59] & ~mbist_run;
t_p_s_2 & data_2[59] & ~mbist_run;
assign legal_data_in_page_size = // 0000, 0001, 0011, 0101
((~data_1[3] & ~data_1[2] & ~data_1[1]) | // 0000, 0001
(~data_1[3] & ~data_1[2] & data_1[0]) | // 0001, 0011
(~data_1[3] & ~data_1[1] & data_1[0]) ) | // 0001, 0101
(~(wr_itlb_data_in_2 | wr_dtlb_data_in_2 |
wr_itlb_data_access_2 | wr_dtlb_data_access_2));
assign clear_data_in_write_[7:0] =
({8 {legal_data_in_page_size}} & wr_tid_dec[7:0]) |
assign legal_tsb_cfg_page_size = // 0000, 0001, 0011, 0101
(~data_1[7] & ~data_1[6] & ~data_1[5]) | // 0000, 0001
(~data_1[7] & ~data_1[6] & data_1[4]) | // 0001, 0011
(~data_1[7] & ~data_1[5] & data_1[4]) | // 0001, 0101
data_2[59]; // read -- don't check for legal size on read!
// fast_dtsb_ptr distinguishes dtsb_ptr from itsb_ptr
(data_1[5] & data_1[4]) | data_1[7];
assign asi_tag_access_sel[2:0] =
{fast_dtsb_ptr, data_1[57:56]};
assign asi_tsb_ptr_req_valid =
itsb_ptr_0 | itsb_ptr_1 | itsb_ptr_2 | itsb_ptr_3 |
dtsb_ptr_0 | dtsb_ptr_1 | dtsb_ptr_2 | dtsb_ptr_3 ;
itsb_ptr_0 | itsb_ptr_1 | itsb_ptr_2 | itsb_ptr_3;
dtsb_ptr_0 | dtsb_ptr_1 | dtsb_ptr_2 | dtsb_ptr_3;
assign asi_tsb_ptr_req[2:0] =
assign asi_tsb_ptr_number[1:0] =
{dtsb_ptr_3 | dtsb_ptr_2 | itsb_ptr_3 | itsb_ptr_2,
dtsb_ptr_3 | dtsb_ptr_1 | itsb_ptr_3 | itsb_ptr_1};
~(rd_tsb_ptr_1 & ~mbist_run);
// MRA diagnostic access at ASI 0x51, addr 0x00 - 0x38
asi & (data_1[55:48] == 8'h51);
// ITLB data access reg at 0x000 - 0x1F8
assign itlb_data_access =
asi & (data_1[55:48] == 8'h55);
assign rd_itlb_data_access =
itlb_data_access & data_1[59];
assign wr_itlb_data_access =
itlb_data_access & ~data_1[59];
// ITLB tag read reg at 0x000 - 0x1F8
asi & (data_1[55:48] == 8'h56);
assign rd_itlb_tag_read =
itlb_tag_read & data_1[59];
// IMMU demap at address 0x0 (data holds command)
asi & (data_1[55:48] == 8'h57) & legal_i_demap;
immu_demap & ~data_1[59];
~data_1[4]; // primary, nucleus
// DMMU demap at address 0x0 (data holds command)
asi & (data_1[55:48] == 8'h5f) & legal_d_demap;
dmmu_demap & ~data_1[59];
~data_1[5] | // primary, secondary
~data_1[4]; // primary, nucleus
// DMMU tag target at 0x00, DMMU SFSR at 0x18, DMMU SFAR at 0x20,
// DMMU tag access at 0x30, hwtw_config at 0x40, partition ID at 0x80,
asi & (data_1[55:48] == 8'h58);
// MMU owns ASI 0x58 except sync fault registers (addr 0x18 & 0x20)
assign rd_asi_58_not_sfr =
rd_asi_58 & ((data_1[5:4] == 2'b00) | (data_1[5:4] == 2'b11));
asi_58 & (data_1[7:3] == 5'b00000);
assign rd_dmmu_tag_target =
dmmu_tag_target & data_1[59];
asi_58 & (data_1[7:3] == 5'b00110);
assign rd_dmmu_tag_access =
dmmu_tag_access & data_1[59];
assign wr_dmmu_tag_access =
dmmu_tag_access & ~data_1[59];
asi_58 & (data_1[7:3] == 5'b01000);
asi_58 & (data_1[7:3] == 5'b10000);
partition_id & ~data_1[59];
// Scratchpad diagnostic access at ASI 0x59, addr 0x00 - 0x78
asi & (data_1[55:48] == 8'h59);
sca_diag & ~data_1[6] & data_1[59];
sca_diag & data_1[6] & data_1[59];
// DTLB data in reg at 0x00
asi & (data_1[55:48] == 8'h5c);
dtlb_data_in & ~data_1[59];
// DTLB data access reg at 0x000 - 0x1F8
assign dtlb_data_access =
asi & (data_1[55:48] == 8'h5d);
assign rd_dtlb_data_access =
dtlb_data_access & data_1[59];
assign wr_dtlb_data_access =
dtlb_data_access & ~data_1[59];
// DTLB tag read reg at 0x000 - 0x1F8
asi & (data_1[55:48] == 8'h5e);
assign rd_dtlb_tag_read =
dtlb_tag_read & data_1[59];
rd_scratchpad | rd_asi_50 | rd_range_offset | rd_asi_54 |
rd_itlb_data_access | rd_itlb_tag_read | rd_asi_58_not_sfr |
rd_dtlb_data_access | rd_dtlb_tag_read | rd_sca_ecc | rd_sca_data;
// Three classes of register:
// 1. Scratchpad registers
// 2. Registers stored in MMU register array (MRA)
// 3. Individual registers present in MMU
// calculations performed within MMU
// These are stored in SCP
({5 {rd_scratchpad & ~mbist_run}} & {data_1[57:56], data_1[5:3]}) |
({5 {wr_scratchpad_2 & ~mbist_run}} & {data_2[57:56], data_2[5:3]}) |
({5 {rd_sca_ecc & ~mbist_run}} & {data_1[57:56], data_1[5:3]}) |
({5 {rd_sca_data & ~mbist_run}} & {data_1[57:56], data_1[5:3]}) |
({5 { mbist_run}} & mbist_addr[4:0] ) ;
assign scp_rd_en_2[1:0] =
{2 {rd_scratchpad_2 & ~mbist_run}} & {data_2[58], ~data_2[58]};
({2 {wr_scratchpad_2 & ~mbist_run}} & {data_2[58], ~data_2[58]}) |
({2 {mbist_run}} & {mbist_scp1_wr_en, mbist_scp0_wr_en}) ;
assign rd_sca_data_en_2[1:0] =
{2 {rd_sca_data_2 & ~mbist_run}} & {data_2[58], ~data_2[58]};
assign rd_sca_ecc_en_2[1:0] =
{2 {rd_sca_ecc_2 & ~mbist_run}} & {data_2[58], ~data_2[58]};
mmu_asi_ctl_msff_ctl_macro__width_5 scp_ctl_lat (
.scan_in(scp_ctl_lat_scanin),
.scan_out(scp_ctl_lat_scanout),
rd_scratchpad_2 | rd_scratchpad_3;
assign rd_scratchpad_4_in =
rd_scratchpad_3 & check_ecc;
mmu_asi_ctl_msff_ctl_macro__width_1 rd_scratchpad_4_lat (
.scan_in(rd_scratchpad_4_lat_scanin),
.scan_out(rd_scratchpad_4_lat_scanout),
.din (rd_scratchpad_4_in ),
.dout (rd_scratchpad_4 ),
assign asi_scp_addr[4:0] =
assign asi_scp_wr_en[1:0] =
({2 {(rd_scratchpad | rd_sca_ecc | rd_sca_data) & ~mbist_run}} &
{data_1[58], ~data_1[58]}) |
({2 {mbist_run}} & {mbist_scp1_rd_en, mbist_scp0_rd_en}) ;
assign asi_scp_rd_en[1:0] =
// MMU register array (MRA)
// z TSB cfg 0,1 address 0
// z TSB cfg 2,3 address 1
// nz TSB cfg 0,1 address 2
// nz TSB cfg 2,3 address 3
// Real range, physical offset pair 0 address 4
// Real range, physical offset pair 1 address 5
// Real range, physical offset pair 2 address 6
// Real range, physical offset pair 3 address 7
// Since registers must be reformatted, read takes two cycles
// (read of array and then format of data)
// Note that reads of the TSB pointers are calculations that depend on
// the TSB configuration registers (and therefore read them)
// All registers are written by
assign mra_rd_en_1[1:0] =
{data_1[58], ~data_1[58]} &
{2 {z_tsb_cfg_0 | z_tsb_cfg_1 |
z_tsb_cfg_2 | z_tsb_cfg_3 |
nz_tsb_cfg_0 | nz_tsb_cfg_1 |
nz_tsb_cfg_2 | nz_tsb_cfg_3 |
itsb_ptr_0 | itsb_ptr_1 |
itsb_ptr_2 | itsb_ptr_3 |
dtsb_ptr_0 | dtsb_ptr_1 |
dtsb_ptr_2 | dtsb_ptr_3 |
real_range_0 | real_range_1 |
real_range_2 | real_range_3 |
physical_offset_0 | physical_offset_1 |
physical_offset_2 | physical_offset_3 |
assign mra_rd_addr[4:3] =
assign mra_rd_addr[2] = // 4, 5, 6, 7
real_range_0 | real_range_1 |
real_range_2 | real_range_3 |
physical_offset_0 | physical_offset_1 |
physical_offset_2 | physical_offset_3 |
(rd_mra_parity & data_1[5]);
assign mra_rd_addr0[1] = // 2, 3, 6, 7
nz_tsb_cfg_0 | nz_tsb_cfg_1 |
nz_tsb_cfg_2 | nz_tsb_cfg_3 |
real_range_2 | real_range_3 |
physical_offset_2 | physical_offset_3 |
(rd_mra_parity & data_1[4]);
assign mra_rd_addr1[1] = // 2, 3, 6, 7
nz_tsb_cfg_0 | nz_tsb_cfg_1 |
nz_tsb_cfg_2 | nz_tsb_cfg_3 |
real_range_2 | real_range_3 |
physical_offset_2 | physical_offset_3 |
(rd_mra_parity & data_1[4]);
assign mra_rd_addr[0] = // 1, 3, 5, 7
z_tsb_cfg_2 | z_tsb_cfg_3 |
nz_tsb_cfg_2 | nz_tsb_cfg_3 |
itsb_ptr_2 | itsb_ptr_3 |
dtsb_ptr_2 | dtsb_ptr_3 |
real_range_1 | real_range_3 |
physical_offset_1 | physical_offset_3 |
(rd_mra_parity & data_1[3]);
assign mra_rd_addr0[4:2] =
assign mra_rd_addr1[4:2] =
mra_rd_addr0[1] | mra_rd_addr1[1];
assign mra_addr_sel_rd[1:0] =
mra_rd_en_1[1:0] & {2 {~mbist_run}};
~mra_rd_en_1[1:0] & {2 {~mbist_run}};
// Prevent any HW TW access to MRA when tsb ptr read occurs
assign mra_addr_sel_hw_tw[1:0] =
htc_mra_rd_en[1:0] & mra_avail[1:0] & {2 {~rd_tsb_ptr_1}};
| mra_addr_sel_hw_tw[1:0];
mmu_asi_ctl_msff_ctl_macro__width_1 req_grant_lat (
.scan_in(req_grant_lat_scanin),
.scan_out(req_grant_lat_scanout),
assign asi_mra_req_grant = // To hardware tablewalk
// 0in bits_on -var {mra_addr_sel_rd[01], mra_addr_sel_hw_tw[01], mbist_run} -max 1
// 0in bits_on -var {mra_addr_sel_rd[00], mra_addr_sel_hw_tw[00], mbist_run} -max 1
assign mra_rd_addr_1[4:0] =
({5 {mra_addr_sel_rd [1]}} & mra_rd_addr1 [4:0]) |
({5 {mra_addr_sel_hw_tw[1]}} & htc_mra_addr_in [4:0]) |
({5 {mbist_run }} & mbist_addr_2 [4:0]) ;
assign mra_rd_addr_0[4:0] =
({5 {mra_addr_sel_rd [0]}} & mra_rd_addr0 [4:0]) |
({5 {mra_addr_sel_hw_tw[0]}} & htc_mra_addr_in [4:0]) |
({5 {mbist_run }} & mbist_addr_2 [4:0]) ;
assign asi_mra_rd_addr_1[4:0] =
assign asi_mra_rd_addr_0[4:0] =
// Account for logic in mmu_asd_dp
(asd1_asi_zero_context & data_1[58]) |
(asd0_asi_zero_context & ~data_1[58]) ;
~zero_context & rd_tsb_ptr_1;
mra_rd_addr[1] | tsb_ptr_addr[1];
mmu_asi_ctl_msff_ctl_macro__width_15 mra_addr_lat (
.scan_in(mra_addr_lat_scanin),
.scan_out(mra_addr_lat_scanout),
.dout ({mra_addr_2 [4:0],
assign asi_mra_wr_addr[4:0] =
(mra_addr_4 [4:0] & {5 {~mbist_run}}) |
(mbist_addr_2 [4:0] & {5 { mbist_run}}) ;
( mra_rd_en_1[1:0] & {2 {~mbist_run}}) |
(htc_mra_rd_en [1:0] & {2 {~mbist_run}}) |
({mbist_mra1_rd_en_2, mbist_mra0_rd_en_2} & {2 { mbist_run}}) ;
assign asi_mra_rd_en[1:0] =
assign mra_to_r3_in_in[1:0] =
assign mra_to_r3_in[1:0] =
(pmra_to_r3_in[0] & ~mbist_run) | (mbist_mra0_rd_en_3 & mbist_run)};
mmu_asi_ctl_msff_ctl_macro__width_6 mra_rd_en_lat (
.scan_in(mra_rd_en_lat_scanin),
.scan_out(mra_rd_en_lat_scanout),
.dout ({mra_rd_en_last [1:0],
assign asi_sel_mra_0_in =
assign asi_mra_rd_en_last[1:0] =
assign mra_wr_en_1[1:0] =
mra_addr_sel_rd[1:0] & {2 {~data_1[59]}};
assign mra_wr_en_3_in[1:0] =
{2 {((mra_sel_tsb_cfg_2 & legal_tsb_cfg_page_size) |
assign mra_sel_tsb_cfg_2 =
mra_sel_tsb_cfg_0_2_2 | mra_sel_tsb_cfg_1_3_2;
mmu_asi_ctl_msff_ctl_macro__width_4 mra_wr_en_lat (
.scan_in(mra_wr_en_lat_scanin),
.scan_out(mra_wr_en_lat_scanout),
.din ({mra_wr_en_1 [1:0],
.dout ({mra_wr_en_2 [1:0],
mmu_asi_ctl_msff_ctl_macro__width_2 mra_wr_en_4_lat (
.scan_in(mra_wr_en_4_lat_scanin),
.scan_out(mra_wr_en_4_lat_scanout),
.din (mra_wr_en_3 [1:0] ),
.dout (mra_wr_en_4 [1:0] ),
assign asi_mra_wr_en_next =
(| mra_wr_en_3[1:0]) | mbist_run;
assign mra_wr_en_out[1:0] =
(mra_wr_en_4[1:0] & {2 {~mra_uecc_4 & ~mbist_run}}) |
({mbist_mra1_wr_en_2, mbist_mra0_wr_en_2} & {2 { mbist_run}}) ;
assign asi_mra_wr_en[1:0] =
// Generate controls for readmux and modify cycles
assign mra_sel_tsb_cfg_0_2_1 =
z_tsb_cfg_0 | z_tsb_cfg_2 |
nz_tsb_cfg_0 | nz_tsb_cfg_2 ;
assign mra_sel_tsb_cfg_1_3_1 =
z_tsb_cfg_1 | z_tsb_cfg_3 |
nz_tsb_cfg_1 | nz_tsb_cfg_3 ;
assign mra_sel_real_range_1 =
real_range_0 | real_range_1 | real_range_2 | real_range_3;
assign mra_sel_physical_offset_1 =
physical_offset_0 | physical_offset_1 |
physical_offset_2 | physical_offset_3;
mmu_asi_ctl_msff_ctl_macro__width_8 mra_sel_lat (
.scan_in(mra_sel_lat_scanin),
.scan_out(mra_sel_lat_scanout),
.din ({mra_sel_tsb_cfg_0_2_1,
mra_sel_physical_offset_1,
mra_sel_physical_offset_2}),
.dout ({mra_sel_tsb_cfg_0_2_2,
mra_sel_physical_offset_2,
mra_sel_physical_offset_3}),
assign asi_rd_tsb_cfg_0_2 =
assign asi_rd_tsb_cfg_1_3 =
assign asi_rd_real_range =
assign asi_rd_physical_offset =
mra_sel_physical_offset_3;
mra_sel_tsb_cfg_0_2_3 | mra_sel_tsb_cfg_1_3_3;
assign asi_mra_wr_data[63:0] =
data_2[10] & ~demap_context_2;
// Individual register reads (write controls from cycle 2)
assign rd_tid_dec [7:0] =
{ data_1[58] & data_1[57] & data_1[56],
data_1[58] & data_1[57] & ~data_1[56],
data_1[58] & ~data_1[57] & data_1[56],
data_1[58] & ~data_1[57] & ~data_1[56],
~data_1[58] & data_1[57] & data_1[56],
~data_1[58] & data_1[57] & ~data_1[56],
~data_1[58] & ~data_1[57] & data_1[56],
~data_1[58] & ~data_1[57] & ~data_1[56]};
assign asi_rd_immu_tag_target[7:0] =
{8 {rd_immu_tag_target}} & rd_tid_dec[7:0];
assign asi_rd_immu_tag_access[7:0] =
{8 {rd_immu_tag_access}} & rd_tid_dec[7:0];
assign asi_rd_i_access_target[1:0] =
{2 {rd_immu_tag_target | rd_immu_tag_access}} &
{data_1[58], ~data_1[58]};
assign asi_rd_dmmu_tag_target[7:0] =
{8 {rd_dmmu_tag_target}} & rd_tid_dec[7:0];
assign asi_rd_dmmu_tag_access[7:0] =
{8 {rd_dmmu_tag_access}} & rd_tid_dec[7:0];
assign asi_rd_d_access_target[1:0] =
{2 {rd_dmmu_tag_target | rd_dmmu_tag_access}} &
{data_1[58], ~data_1[58]};
assign asi_rd_access_target[1:0] =
{2 {rd_immu_tag_target | rd_immu_tag_access |
rd_dmmu_tag_target | rd_dmmu_tag_access }} &
{data_1[58], ~data_1[58]};
assign dtlb0_tte_tag[63:0] =
{{16 {1'b0}}, asd0_dtte_tag[47:0]};
assign dtlb1_tte_tag[63:0] =
{{16 {1'b0}}, asd1_dtte_tag[47:0]};
assign scp0_ecc_bus[63:0] =
{{56 {1'b0}}, scp0_ecc[7:0]};
assign scp1_ecc_bus[63:0] =
{{56 {1'b0}}, scp1_ecc[7:0]};
assign mbist_scp0_0[63:0] =
{{32 {1'b0}}, scp0_data[31:0]};
assign mbist_scp0_1[63:0] =
{{32 {1'b0}}, scp0_data[63:32]};
assign mbist_scp0_2[63:0] =
{{32 {1'b0}}, {4 {scp0_ecc[7:0]}}};
assign mbist_scp1_0[63:0] =
{{32 {1'b0}}, scp1_data[31:0]};
assign mbist_scp1_1[63:0] =
{{32 {1'b0}}, scp1_data[63:32]};
assign mbist_scp1_2[63:0] =
{{32 {1'b0}}, {4 {scp1_ecc[7:0]}}};
~(| {use_dtlb_window[1:0], asd_asi_sel[1:0], scp_rd_en_2[1:0],
rd_sca_ecc_en_2[1:0], rd_sca_data_en_2[1:0],
mbist_scp0_rd_en_2, mbist_scp1_rd_en_2, rd_hwtw_config_2,
rd_t_p_c_2, rd_t_p_s_2});
assign asd_asi_sel[1:0] =
{2 {asd_asi_rd_2 & ~mbist_run}} & {data_2[58], ~data_2[58]};
rd_immu_tag_target | rd_immu_tag_access |
rd_dmmu_tag_target | rd_dmmu_tag_access;
// 0in bits_on -var {sel_data_1, use_dtlb_window[01:00], asd_asi_sel[01:00], scp_rd_en_2[01:00], rd_sca_ecc_en_2[01:00], rd_hwtw_config_2, rd_sca_data_en_2[01:00]} -max 1
({64 {sel_data_1 }} & data_1 [63:0]) |
({64 {use_dtlb_window[0] }} & dtlb0_tte_tag [63:0]) |
({64 {use_dtlb_window[1] }} & dtlb1_tte_tag [63:0]) |
({64 {asd_asi_sel[0] }} & asd0_asi_rd_data [63:0]) |
({64 {asd_asi_sel[1] }} & asd1_asi_rd_data [63:0]) |
({64 {scp_rd_en_2[0] }} & scp0_data [63:0]) |
({64 {scp_rd_en_2[1] }} & scp1_data [63:0]) |
({64 {rd_sca_data_en_2[0]}} & scp0_data [63:0]) |
({64 {rd_sca_data_en_2[1]}} & scp1_data [63:0]) |
({64 {rd_sca_ecc_en_2[0] }} & scp0_ecc_bus [63:0]) |
({64 {rd_sca_ecc_en_2[1] }} & scp1_ecc_bus [63:0]) |
({64 {rd_hwtw_config_2 }} & hwtw_config_muxed [63:0]) |
({64 {mbist_scp0_0_rd_en }} & mbist_scp0_0 [63:0]) |
({64 {mbist_scp0_1_rd_en }} & mbist_scp0_1 [63:0]) |
({64 {mbist_scp0_2_rd_en }} & mbist_scp0_2 [63:0]) |
({64 {mbist_scp1_0_rd_en }} & mbist_scp1_0 [63:0]) |
({64 {mbist_scp1_1_rd_en }} & mbist_scp1_1 [63:0]) |
({64 {mbist_scp1_2_rd_en }} & mbist_scp1_2 [63:0]) |
({64 {rd_t_p_c_2 }} & rd_t_p_c_data [63:0]) |
({64 {rd_t_p_s_2 }} & rd_t_p_s_data [63:0]) ;
// For muxing of ECC bits in mmu_sel_dp
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
// pipe the packets and decoded control information
mmu_asi_ctl_msff_ctl_macro__width_64 stg2_data_lat (
.scan_in(stg2_data_lat_scanin),
.scan_out(stg2_data_lat_scanout),
.din (data_2_in [63:0] ),
assign asi_mbd_scp_data[31:0] =
mmu_asi_ctl_msff_ctl_macro__width_16 stg2_ctl_lat (
.scan_in(stg2_ctl_lat_scanin),
.scan_out(stg2_ctl_lat_scanout),
// send the store data out to the unit. Store data is in stage1 when control
assign asi_seg_wr_data [63:0] =
assign asi_wr_data [63:0] =
(data_1 [63:0] & {64 {~mbist_run}}) |
(mbist_wr_data [63:0] & {64 { mbist_run}}) ;
assign wr_tid_dec [7:0] =
{ data_2[58] & data_2[57] & data_2[56],
data_2[58] & data_2[57] & ~data_2[56],
data_2[58] & ~data_2[57] & data_2[56],
data_2[58] & ~data_2[57] & ~data_2[56],
~data_2[58] & data_2[57] & data_2[56],
~data_2[58] & data_2[57] & ~data_2[56],
~data_2[58] & ~data_2[57] & data_2[56],
~data_2[58] & ~data_2[57] & ~data_2[56]};
assign a_wr_immu_tag_access[7:0] =
{8 { wr_immu_tag_access_2}} & wr_tid_dec[7:0] ;
assign asi_wr_immu_tag_access[7:0] =
a_wr_immu_tag_access[7:0];
assign a_wr_itlb_data_in[7:0] =
{8 { wr_itlb_data_in_2 & legal_data_in_page_size}} & wr_tid_dec[7:0] ;
assign asi_wr_itlb_data_in[7:0] =
assign a_wr_itlb_data_access[7:0] =
{8 { wr_itlb_data_access_2 & legal_data_in_page_size}} &
assign asi_wr_itlb_data_access[7:0] =
a_wr_itlb_data_access[7:0];
assign a_wr_immu_demap[7:0] =
{8 {wr_immu_demap_2}} & wr_tid_dec[7:0] ;
assign asi_wr_immu_demap[7:0] =
// Demap uses address, not data, so use data_2 here
assign asi_wr_immu_demap_p[7:0] =
{8 {wr_immu_demap_2 & ~data_2[5] & ~data_2[4] }} & wr_tid_dec[7:0] ;
assign asi_wr_immu_demap_n[7:0] =
{8 {wr_immu_demap_2 & (data_2[5] | data_2[4])}} & wr_tid_dec[7:0] ;
assign a_wr_dmmu_tag_access[7:0] =
{8 { wr_dmmu_tag_access_2}} & wr_tid_dec[7:0] ;
assign asi_wr_dmmu_tag_access[7:0] =
a_wr_dmmu_tag_access[7:0];
assign a_wr_dtlb_data_in[7:0] =
{8 { wr_dtlb_data_in_2 & legal_data_in_page_size}} & wr_tid_dec[7:0] ;
assign asi_wr_dtlb_data_in[7:0] =
assign a_wr_dtlb_data_access[7:0] =
{8 { wr_dtlb_data_access_2 & legal_data_in_page_size}} &
assign asi_wr_dtlb_data_access[7:0] =
a_wr_dtlb_data_access[7:0];
assign asi_wr_partition_id[7:0] =
{8 {wr_partition_id_2}} & wr_tid_dec[7:0] ;
assign a_wr_dmmu_demap[7:0] =
{8 {wr_dmmu_demap_2}} & wr_tid_dec[7:0] ;
assign asi_wr_dmmu_demap[7:0] =
// Demap uses address, not data, so use data_2 here
assign asi_wr_dmmu_demap_p[7:0] =
{8 {wr_dmmu_demap_2 & ~data_2[5] & ~data_2[4] }} & wr_tid_dec[7:0] ;
assign asi_wr_dmmu_demap_s_n[7:0] =
{8 {wr_dmmu_demap_2 & (data_2[5] | data_2[4])}} & wr_tid_dec[7:0] ;
assign asi_dmmu_demap_s =
// Write of p_context shadows for immu_tag_access reg
assign asi_wr_p_context_0[7:0] =
{8 {wr_p_context_0_2}} & wr_tid_dec[7:0];
assign asi_p_context_0_en[1:0] =
{2 {wr_p_context_0_2}} & {data_2[58], ~data_2[58]};
assign rd_hwtw_config_2 =
hwtwconfig_2 & data_2[59] & ~mbist_run;
assign rd_hwtw_config_dec =
{8 {hwtwconfig_2 & data_2[59]}} & wr_tid_dec[7:0];
assign wr_hwtw_config_dec =
{8 {hwtwconfig_2 & ~data_2[59]}} & wr_tid_dec[7:0];
assign suppress_write_2 =
((wr_itlb_data_in_2 | wr_dtlb_data_in_2 |
wr_itlb_data_access_2 | wr_dtlb_data_access_2) &
~legal_data_in_page_size) |
((| mra_to_r3_in[1:0]) & mra_sel_tsb_cfg_2 & ~legal_tsb_cfg_page_size);
mmu_asi_ctl_msff_ctl_macro__width_1 dae_req_lat (
.scan_in(dae_req_lat_scanin),
.scan_out(dae_req_lat_scanout),
.din (suppress_write_2 ),
.dout (suppress_write_3 ),
assign mmu_dae_tid[2:0] =
// Real bit for data_in and data_access is encoded in address bit 10
assign asi_data_in_real =
// Set error bit for ECC problems
| (tlu_ceter_pscce[7:0] &
{ data_2[58] & data_2[57] & data_2[56],
data_2[58] & data_2[57] & ~data_2[56],
data_2[58] & ~data_2[57] & data_2[56],
data_2[58] & ~data_2[57] & ~data_2[56],
~data_2[58] & data_2[57] & data_2[56],
~data_2[58] & data_2[57] & ~data_2[56],
~data_2[58] & ~data_2[57] & data_2[56],
~data_2[58] & ~data_2[57] & ~data_2[56]});
mmu_asi_ctl_msff_ctl_macro__width_1 check_ecc_lat (
.scan_in(check_ecc_lat_scanin),
.scan_out(check_ecc_lat_scanout),
assign pmra_to_r4_in[1:0] =
pmra_to_r3[1:0] & {2 {check_ecc}};
mmu_asi_ctl_msff_ctl_macro__width_2 pmra_to_r4_lat (
.scan_in(pmra_to_r4_lat_scanin),
.scan_out(pmra_to_r4_lat_scanout),
.din (pmra_to_r4_in [1:0] ),
.dout (pmra_to_r4 [1:0] ),
(sel_scac & rd_scratchpad_4) ;
(sel_scau & rd_scratchpad_4) |
(mel0_parity_err & pmra_to_r4[0] ) |
(mel1_parity_err & pmra_to_r4[1] ) ;
(mel0_parity_err & pmra_to_r4[0] ) |
(mel1_parity_err & pmra_to_r4[1] ) ;
mmu_asi_ctl_msff_ctl_macro__width_3 tid_4_lat (
.scan_in(tid_4_lat_scanin),
.scan_out(tid_4_lat_scanout),
assign mmu_asi_tid[2:0] =
assign mmu_asi_mra_not_sca =
mmu_asi_ctl_msff_ctl_macro__width_3 sca_index_lat (
.scan_in(sca_index_lat_scanin),
.scan_out(sca_index_lat_scanout),
.dout (sca_index [2:0] ),
assign mmu_asi_index[2:0] =
({3 {~rd_scratchpad_4}} & mra_addr_4[2:0]) |
({3 { rd_scratchpad_4}} & sca_index [2:0]) ;
assign rngf_cdbus_2[64:0] =
{1'b0, ase_mra_rd_data[63:0]};
assign mra_tsb_cfg[64:0] =
{1'b0, tsb_hwtw_en_3, ase_mra_rd_data[62:0]};
assign mra_parity[64:0] =
(mel0_parity[1:0] & {2 {~data_3[59]}}) |
(mel1_parity[1:0] & {2 { data_3[59]}}) };
assign dtlb0_tte_data[64:0] =
{1'b0, {8 {1'b0}}, 1'b0, asd0_dtte_data[54:0]};
assign dtlb1_tte_data[64:0] =
{1'b0, {8 {1'b0}}, 1'b0, asd1_dtte_data[54:0]};
assign tsb_ptr_data[64:0] =
{1'b0, {24 {1'b0}}, htd_tsbptr[39:4], {4 {1'b0}}};
(| pmra_to_r3[1:0]) & data_3[59];
mra_to_r3 & ~rd_tsb_cfg_3 & ~rd_mra_parity_3 & ~rd_tsb_ptr_3;
mra_to_r3 & rd_tsb_cfg_3 & ~rd_mra_parity_3 & ~rd_tsb_ptr_3;
~(| ({use_dtlb_window[1:0], mra_not_tsb_cfg, mra_sel_tsb_cfg,
rd_mra_parity_3, rd_tsb_ptr_3}));
// 0in bits_on -var {use_dtlb_window[01:00], sel_cdbus_2, mra_not_tsb_cfg, mra_sel_tsb_cfg, rd_mra_parity_3, rd_tsb_ptr_3} -max 1
({65 {use_dtlb_window[0]}} & dtlb0_tte_data [64:0]) |
({65 {use_dtlb_window[1]}} & dtlb1_tte_data [64:0]) |
({65 {sel_cdbus_2 }} & rngf_cdbus_2 [64:0]) |
({65 {mra_not_tsb_cfg }} & mra_data [64:0]) |
({65 {mra_sel_tsb_cfg }} & mra_tsb_cfg [64:0]) |
({65 {rd_mra_parity_3 }} & mra_parity [64:0]) |
({65 {rd_tsb_ptr_3 }} & tsb_ptr_data [64:0]) ;
/////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////
// Mux previous results with TSA reads
mmu_asi_ctl_msff_ctl_macro__width_65 rng_stg3 (
.scan_in(rng_stg3_scanin),
.scan_out(rng_stg3_scanout),
.din (data_3_in [64:0] ),
assign asi_rd_data[63:0] =
mmu_asi_ctl_msff_ctl_macro__width_3 stg3_ctl_lat (
.scan_in(stg3_ctl_lat_scanin),
.scan_out(stg3_ctl_lat_scanout),
mmu_asi_ctl_msff_ctl_macro__width_1 asi_read_lat (
.scan_in(asi_read_lat_scanin),
.scan_out(asi_read_lat_scanout),
assign mmu_asi_data[64:0] =
data_3[62] | suppress_write_3,
(data_3[49:48] & ~{2 {suppress_write_3}}) | {1'b0, suppress_write_3},
mmu_asi_rd_3 | dtlb_window_used | dtlb_window_used_last |
//////////////////////////////////////////////////////////////////////
// Once a data_in or data_access register write occurs, the tag and data
// must be transmitted to the TLB and written.
assign idata_in_data_access =
wr_itlb_data_in | wr_itlb_data_access | wr_immu_demap;
assign ddata_in_data_access =
wr_dtlb_data_in | wr_dtlb_data_access | wr_dmmu_demap;
(rd_tid_dec[7:0] & {8 {idata_in_data_access}}) |
(htc_wr_itlb_data_in[7:0]) |
(rd_itte [7:0] & ~tlu_release_tte[7:0]);
(rd_tid_dec[7:0] & {8 {ddata_in_data_access}}) |
(prd_dtte [7:0] & clear_data_in_write_[7:0] & ~wrote_dtlb_in[7:0]);
assign sel_rd_dtte_hwtw_in =
assign rd_dtte_hwtw_in[7:0] =
(htc_wr_dtlb_data_in[7:0]) |
(rd_dtte_hwtw[7:0] & ~wrote_dtlb_in[7:0]) ;
mmu_asi_ctl_msff_ctl_macro__width_25 rd_tte_lat (
.scan_in(rd_tte_lat_scanin),
.scan_out(rd_tte_lat_scanout),
mmu_asi_ctl_msff_ctl_macro__width_1 idata_in_data_access_2_lat (
.scan_in(idata_in_data_access_2_lat_scanin),
.scan_out(idata_in_data_access_2_lat_scanout),
.din (idata_in_data_access ),
.dout (idata_in_data_access_2 ),
prd_itte[7:0] & clear_data_in_write_[7:0];
({8 {~sel_rd_dtte_hwtw}} & prd_dtte[7:0] &
clear_data_in_write_[7:0]) |
({8 { sel_rd_dtte_hwtw}} & rd_dtte_hwtw[7:0] &
{{4 {dtlb_window[1]}}, {4 {dtlb_window[0]}}});
assign rd_itte_last_in[7:0] =
(rd_itte[7:0] & ~tlu_release_tte[7:0]) | htc_wr_itlb_data_in[7:0];
// data must be read same cycle as tlu_release_tte, but no time to control
// tag must be read the cycle after tlu_release_tte
assign rd_itte_last_last_in[7:0] =
{rd_itte_last[7] & ~(| rd_itte_last[6:0]),
rd_itte_last[6] & ~(| rd_itte_last[5:0]),
rd_itte_last[5] & ~(| rd_itte_last[4:0]),
rd_itte_last[4] & ~(| rd_itte_last[3:0]),
rd_itte_last[3] & ~(| rd_itte_last[2:0]),
rd_itte_last[2] & ~(| rd_itte_last[1:0]),
rd_itte_last[1] & ~( rd_itte_last[0 ]),
assign rd_itte_data_in[7:0] =
rd_itte_last_last[7:0] & {8 {~(| tlu_release_tte[7:0])}};
assign rd_itte_tag_in[7:0] =
rd_itte_data[7:0] & tlu_release_tte[7:0];
mmu_asi_ctl_msff_ctl_macro__width_32 rd_itte_lat (
.scan_in(rd_itte_lat_scanin),
.scan_out(rd_itte_lat_scanout),
.din ({rd_itte_last_in [7:0],
rd_itte_last_last_in [7:0],
.dout ({prd_itte_last [7:0],
assign rd_itte_last[7:0] =
prd_itte_last[7:0] & ~tlu_release_tte[7:0];
assign asi_rd_itte_tag[7:0] =
assign asi_rd_itte_data[7:0] =
assign asi_rd_dtte[6:0] =
({7 {~sel_rd_dtte_hwtw}} & prd_dtte [6:0]) |
({7 { sel_rd_dtte_hwtw}} & rd_dtte_hwtw[6:0]) ;
// Send ITLB reload request to TLU; only assert for one cycle
// Sent in cycle 2 of access
assign mmu_write_itlb[7:0] =
{8 {idata_in_data_access_2 & legal_data_in_page_size}}) |
htc_wr_itlb_data_in[7:0];
// Detect hole sufficient for DTLB reload
// If three cycles occur without a control packet, then DTLB write can use the
// last two cycles; the last two cycles are the DTLB window
// The tag and data will be loaded into the stage 2 and 3 flops.
// Bus is idle on a given cycle if ctl and valid are not both 1
assign dtlb_window[1:0] =
{2 {~(ctl_1 & data_1[63]) & ~(ctl_2 & data_2[63]) &
~(ctl_3 & data_3[63]) & ~dtlb_window_used_last}};
// 0in req_ack -req wr_dtlb_data_in -ack (| {use_dtlb_window[01:00], (wr_itlb_data_in_2 | wr_itlb_data_access_2 | wr_dtlb_data_in_2 | wr_dtlb_data_access_2) & ~legal_data_in_page_size}) -single_ack off -message "Multiple DTLB updates outstanding for ASI bus from MMU to LSU"
assign use_dtlb_window[1:0] =
{(| rd_dtte[7:4]) & ~(| rd_dtte[3:0]),
(| rd_dtte[3:0])} & {2 {~mbist_run}};
assign dtlb_window_used =
mmu_asi_ctl_msff_ctl_macro__width_1 dtlb_window_used_last_lat (
.scan_in(dtlb_window_used_last_lat_scanin),
.scan_out(dtlb_window_used_last_lat_scanout),
.din (dtlb_window_used ),
.dout (dtlb_window_used_last ),
assign wrote_dtlb_in[7] =
use_dtlb_window[1] & rd_dtte[7] & ~(| rd_dtte[6:4]);
assign wrote_dtlb_in[6] =
use_dtlb_window[1] & rd_dtte[6] & ~(| rd_dtte[5:4]);
assign wrote_dtlb_in[5] =
use_dtlb_window[1] & rd_dtte[5] & ~ rd_dtte[4 ] ;
assign wrote_dtlb_in[4] =
use_dtlb_window[1] & rd_dtte[4] ;
assign wrote_dtlb_in[3] =
use_dtlb_window[0] & rd_dtte[3] & ~(| rd_dtte[2:0]);
assign wrote_dtlb_in[2] =
use_dtlb_window[0] & rd_dtte[2] & ~(| rd_dtte[1:0]);
assign wrote_dtlb_in[1] =
use_dtlb_window[0] & rd_dtte[1] & ~ rd_dtte[0 ] ;
assign wrote_dtlb_in[0] =
use_dtlb_window[0] & rd_dtte[0] ;
// 0in assert_follower -leader ($0in_rising_edge(prd_dtte[07:00]&clear_data_in_write_[07:00])) -follower ($0in_rising_edge(wrote_dtlb_in[07:00])) -min 2 -max 2 -message "DTLB updates are being reordered!"
mmu_asi_ctl_msff_ctl_macro__width_4 wrote_dtlb_tg1_lat (
.scan_in(wrote_dtlb_tg1_lat_scanin),
.scan_out(wrote_dtlb_tg1_lat_scanout),
.din (wrote_dtlb_in [7:4] ),
.dout (wrote_dtlb [7:4] ),
mmu_asi_ctl_msff_ctl_macro__width_4 wrote_dtlb_tg0_lat (
.scan_in(wrote_dtlb_tg0_lat_scanin),
.scan_out(wrote_dtlb_tg0_lat_scanout),
.din (wrote_dtlb_in [3:0] ),
.dout (wrote_dtlb [3:0] ),
assign reload_done_in[7:0] =
htc_wr_itlb_data_in[7:0] |
(rd_dtte_hwtw[7:0] & wrote_dtlb_in[7:0]) ;
mmu_asi_ctl_msff_ctl_macro__width_4 reload_done_tg1_lat (
.scan_in(reload_done_tg1_lat_scanin),
.scan_out(reload_done_tg1_lat_scanout),
.din (reload_done_in [7:4] ),
.dout (reload_done [7:4] ),
mmu_asi_ctl_msff_ctl_macro__width_4 reload_done_tg0_lat (
.scan_in(reload_done_tg0_lat_scanin),
.scan_out(reload_done_tg0_lat_scanout),
.din (reload_done_in [3:0] ),
.dout (reload_done [3:0] ),
assign mmu_reload_done[7:0] =
// Block dispatch for DTLB reload
//--------------------------------------------------------------------
// mmu_dtlb_reload_stall X X
assign dtlb_reload_stall_in =
(| {wrote_dtlb[7:0], dtlb_reload});
mmu_asi_ctl_msff_ctl_macro__width_1 dtlb_reload_stall_lat (
.scan_in(dtlb_reload_stall_lat_scanin),
.scan_out(dtlb_reload_stall_lat_scanout),
.din (dtlb_reload_stall_in ),
.dout (dtlb_reload_stall ),
assign mmu_dtlb_reload_stall =
mmu_asi_ctl_msff_ctl_macro__width_1 dtlb_reload_lat (
.scan_in(dtlb_reload_lat_scanin),
.scan_out(dtlb_reload_lat_scanout),
//////////////////////////////////////////////////////////////////////
// Maintain hardware tablewalk enables
// Pipe write signals to stage 4 to match write of MRA
assign wr_tsb_cfg_enc[3:0] =
{wr_z_tsb_cfg_0 | wr_z_tsb_cfg_1 | wr_z_tsb_cfg_2 | wr_z_tsb_cfg_3 |
wr_nz_tsb_cfg_0 | wr_nz_tsb_cfg_1 | wr_nz_tsb_cfg_2 | wr_nz_tsb_cfg_3 ,
wr_nz_tsb_cfg_0 | wr_nz_tsb_cfg_1 | wr_nz_tsb_cfg_2 | wr_nz_tsb_cfg_3 ,
wr_z_tsb_cfg_2 | wr_z_tsb_cfg_3 | wr_nz_tsb_cfg_2 | wr_nz_tsb_cfg_3 ,
wr_z_tsb_cfg_1 | wr_z_tsb_cfg_3 | wr_nz_tsb_cfg_1 | wr_nz_tsb_cfg_3
mmu_asi_ctl_msff_ctl_macro__width_12 wr_tsb_cfg_lat (
.scan_in(wr_tsb_cfg_lat_scanin),
.scan_out(wr_tsb_cfg_lat_scanout),
.din ({wr_tsb_cfg_enc [3:0],
wr_tsb_cfg_enc_3 [3:0]}),
.dout ({wr_tsb_cfg_enc_2 [3:0],
wr_tsb_cfg_enc_4 [3:0]}),
assign wr_z_tsb_cfg_3_4 =
wr_tsb_cfg_enc_4[3] & ~wr_tsb_cfg_enc_4[2] &
wr_tsb_cfg_enc_4[1] & wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);
assign wr_z_tsb_cfg_2_4 =
wr_tsb_cfg_enc_4[3] & ~wr_tsb_cfg_enc_4[2] &
wr_tsb_cfg_enc_4[1] & ~wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);
assign wr_z_tsb_cfg_1_4 =
wr_tsb_cfg_enc_4[3] & ~wr_tsb_cfg_enc_4[2] &
~wr_tsb_cfg_enc_4[1] & wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);
assign wr_z_tsb_cfg_0_4 =
wr_tsb_cfg_enc_4[3] & ~wr_tsb_cfg_enc_4[2] &
~wr_tsb_cfg_enc_4[1] & ~wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);
assign wr_nz_tsb_cfg_3_4 =
wr_tsb_cfg_enc_4[3] & wr_tsb_cfg_enc_4[2] &
wr_tsb_cfg_enc_4[1] & wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);
assign wr_nz_tsb_cfg_2_4 =
wr_tsb_cfg_enc_4[3] & wr_tsb_cfg_enc_4[2] &
wr_tsb_cfg_enc_4[1] & ~wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);
assign wr_nz_tsb_cfg_1_4 =
wr_tsb_cfg_enc_4[3] & wr_tsb_cfg_enc_4[2] &
~wr_tsb_cfg_enc_4[1] & wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);
assign wr_nz_tsb_cfg_0_4 =
wr_tsb_cfg_enc_4[3] & wr_tsb_cfg_enc_4[2] &
~wr_tsb_cfg_enc_4[1] & ~wr_tsb_cfg_enc_4[0] & (| mra_wr_en_out[1:0]);
{ tid_4[2] & tid_4[1] & tid_4[0],
tid_4[2] & tid_4[1] & ~tid_4[0],
tid_4[2] & ~tid_4[1] & tid_4[0],
tid_4[2] & ~tid_4[1] & ~tid_4[0],
~tid_4[2] & tid_4[1] & tid_4[0],
~tid_4[2] & tid_4[1] & ~tid_4[0],
~tid_4[2] & ~tid_4[1] & tid_4[0],
~tid_4[2] & ~tid_4[1] & ~tid_4[0]};
(t7_e_z [3] & ~(wr_z_tsb_cfg_3_4 & tid_dec_4[7])) |
(data_3 [63] & (wr_z_tsb_cfg_3_4 & tid_dec_4[7])) ;
(t7_e_z [2] & ~(wr_z_tsb_cfg_2_4 & tid_dec_4[7])) |
(data_3 [63] & (wr_z_tsb_cfg_2_4 & tid_dec_4[7])) ;
(t7_e_z [1] & ~(wr_z_tsb_cfg_1_4 & tid_dec_4[7])) |
(data_3 [63] & (wr_z_tsb_cfg_1_4 & tid_dec_4[7])) ;
(t7_e_z [0] & ~(wr_z_tsb_cfg_0_4 & tid_dec_4[7])) |
(data_3 [63] & (wr_z_tsb_cfg_0_4 & tid_dec_4[7])) ;
(t7_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[7])) |
(data_3 [63] & (wr_nz_tsb_cfg_3_4 & tid_dec_4[7])) ;
(t7_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[7])) |
(data_3 [63] & (wr_nz_tsb_cfg_2_4 & tid_dec_4[7])) ;
(t7_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[7])) |
(data_3 [63] & (wr_nz_tsb_cfg_1_4 & tid_dec_4[7])) ;
(t7_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[7])) |
(data_3 [63] & (wr_nz_tsb_cfg_0_4 & tid_dec_4[7])) ;
(t6_e_z [3] & ~(wr_z_tsb_cfg_3_4 & tid_dec_4[6])) |
(data_3 [63] & (wr_z_tsb_cfg_3_4 & tid_dec_4[6])) ;
(t6_e_z [2] & ~(wr_z_tsb_cfg_2_4 & tid_dec_4[6])) |
(data_3 [63] & (wr_z_tsb_cfg_2_4 & tid_dec_4[6])) ;
(t6_e_z [1] & ~(wr_z_tsb_cfg_1_4 & tid_dec_4[6])) |
(data_3 [63] & (wr_z_tsb_cfg_1_4 & tid_dec_4[6])) ;
(t6_e_z [0] & ~(wr_z_tsb_cfg_0_4 & tid_dec_4[6])) |
(data_3 [63] & (wr_z_tsb_cfg_0_4 & tid_dec_4[6])) ;
(t6_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[6])) |
(data_3 [63] & (wr_nz_tsb_cfg_3_4 & tid_dec_4[6])) ;
(t6_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[6])) |
(data_3 [63] & (wr_nz_tsb_cfg_2_4 & tid_dec_4[6])) ;
(t6_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[6])) |
(data_3 [63] & (wr_nz_tsb_cfg_1_4 & tid_dec_4[6])) ;
(t6_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[6])) |
(data_3 [63] & (wr_nz_tsb_cfg_0_4 & tid_dec_4[6])) ;
(t5_e_z [3] & ~(wr_z_tsb_cfg_3_4 & tid_dec_4[5])) |
(data_3 [63] & (wr_z_tsb_cfg_3_4 & tid_dec_4[5])) ;
(t5_e_z [2] & ~(wr_z_tsb_cfg_2_4 & tid_dec_4[5])) |
(data_3 [63] & (wr_z_tsb_cfg_2_4 & tid_dec_4[5])) ;
(t5_e_z [1] & ~(wr_z_tsb_cfg_1_4 & tid_dec_4[5])) |
(data_3 [63] & (wr_z_tsb_cfg_1_4 & tid_dec_4[5])) ;
(t5_e_z [0] & ~(wr_z_tsb_cfg_0_4 & tid_dec_4[5])) |
(data_3 [63] & (wr_z_tsb_cfg_0_4 & tid_dec_4[5])) ;
(t5_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[5])) |
(data_3 [63] & (wr_nz_tsb_cfg_3_4 & tid_dec_4[5])) ;
(t5_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[5])) |
(data_3 [63] & (wr_nz_tsb_cfg_2_4 & tid_dec_4[5])) ;
(t5_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[5])) |
(data_3 [63] & (wr_nz_tsb_cfg_1_4 & tid_dec_4[5])) ;
(t5_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[5])) |
(data_3 [63] & (wr_nz_tsb_cfg_0_4 & tid_dec_4[5])) ;
(t4_e_z [3] & ~(wr_z_tsb_cfg_3_4 & tid_dec_4[4])) |
(data_3 [63] & (wr_z_tsb_cfg_3_4 & tid_dec_4[4])) ;
(t4_e_z [2] & ~(wr_z_tsb_cfg_2_4 & tid_dec_4[4])) |
(data_3 [63] & (wr_z_tsb_cfg_2_4 & tid_dec_4[4])) ;
(t4_e_z [1] & ~(wr_z_tsb_cfg_1_4 & tid_dec_4[4])) |
(data_3 [63] & (wr_z_tsb_cfg_1_4 & tid_dec_4[4])) ;
(t4_e_z [0] & ~(wr_z_tsb_cfg_0_4 & tid_dec_4[4])) |
(data_3 [63] & (wr_z_tsb_cfg_0_4 & tid_dec_4[4])) ;
(t4_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[4])) |
(data_3 [63] & (wr_nz_tsb_cfg_3_4 & tid_dec_4[4])) ;
(t4_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[4])) |
(data_3 [63] & (wr_nz_tsb_cfg_2_4 & tid_dec_4[4])) ;
(t4_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[4])) |
(data_3 [63] & (wr_nz_tsb_cfg_1_4 & tid_dec_4[4])) ;
(t4_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[4])) |
(data_3 [63] & (wr_nz_tsb_cfg_0_4 & tid_dec_4[4])) ;
(t3_e_z [3] & ~(wr_z_tsb_cfg_3_4 & tid_dec_4[3])) |
(data_3 [63] & (wr_z_tsb_cfg_3_4 & tid_dec_4[3])) ;
(t3_e_z [2] & ~(wr_z_tsb_cfg_2_4 & tid_dec_4[3])) |
(data_3 [63] & (wr_z_tsb_cfg_2_4 & tid_dec_4[3])) ;
(t3_e_z [1] & ~(wr_z_tsb_cfg_1_4 & tid_dec_4[3])) |
(data_3 [63] & (wr_z_tsb_cfg_1_4 & tid_dec_4[3])) ;
(t3_e_z [0] & ~(wr_z_tsb_cfg_0_4 & tid_dec_4[3])) |
(data_3 [63] & (wr_z_tsb_cfg_0_4 & tid_dec_4[3])) ;
(t3_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[3])) |
(data_3 [63] & (wr_nz_tsb_cfg_3_4 & tid_dec_4[3])) ;
(t3_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[3])) |
(data_3 [63] & (wr_nz_tsb_cfg_2_4 & tid_dec_4[3])) ;
(t3_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[3])) |
(data_3 [63] & (wr_nz_tsb_cfg_1_4 & tid_dec_4[3])) ;
(t3_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[3])) |
(data_3 [63] & (wr_nz_tsb_cfg_0_4 & tid_dec_4[3])) ;
(t2_e_z [3] & ~(wr_z_tsb_cfg_3_4 & tid_dec_4[2])) |
(data_3 [63] & (wr_z_tsb_cfg_3_4 & tid_dec_4[2])) ;
(t2_e_z [2] & ~(wr_z_tsb_cfg_2_4 & tid_dec_4[2])) |
(data_3 [63] & (wr_z_tsb_cfg_2_4 & tid_dec_4[2])) ;
(t2_e_z [1] & ~(wr_z_tsb_cfg_1_4 & tid_dec_4[2])) |
(data_3 [63] & (wr_z_tsb_cfg_1_4 & tid_dec_4[2])) ;
(t2_e_z [0] & ~(wr_z_tsb_cfg_0_4 & tid_dec_4[2])) |
(data_3 [63] & (wr_z_tsb_cfg_0_4 & tid_dec_4[2])) ;
(t2_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[2])) |
(data_3 [63] & (wr_nz_tsb_cfg_3_4 & tid_dec_4[2])) ;
(t2_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[2])) |
(data_3 [63] & (wr_nz_tsb_cfg_2_4 & tid_dec_4[2])) ;
(t2_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[2])) |
(data_3 [63] & (wr_nz_tsb_cfg_1_4 & tid_dec_4[2])) ;
(t2_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[2])) |
(data_3 [63] & (wr_nz_tsb_cfg_0_4 & tid_dec_4[2])) ;
(t1_e_z [3] & ~(wr_z_tsb_cfg_3_4 & tid_dec_4[1])) |
(data_3 [63] & (wr_z_tsb_cfg_3_4 & tid_dec_4[1])) ;
(t1_e_z [2] & ~(wr_z_tsb_cfg_2_4 & tid_dec_4[1])) |
(data_3 [63] & (wr_z_tsb_cfg_2_4 & tid_dec_4[1])) ;
(t1_e_z [1] & ~(wr_z_tsb_cfg_1_4 & tid_dec_4[1])) |
(data_3 [63] & (wr_z_tsb_cfg_1_4 & tid_dec_4[1])) ;
(t1_e_z [0] & ~(wr_z_tsb_cfg_0_4 & tid_dec_4[1])) |
(data_3 [63] & (wr_z_tsb_cfg_0_4 & tid_dec_4[1])) ;
(t1_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[1])) |
(data_3 [63] & (wr_nz_tsb_cfg_3_4 & tid_dec_4[1])) ;
(t1_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[1])) |
(data_3 [63] & (wr_nz_tsb_cfg_2_4 & tid_dec_4[1])) ;
(t1_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[1])) |
(data_3 [63] & (wr_nz_tsb_cfg_1_4 & tid_dec_4[1])) ;
(t1_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[1])) |
(data_3 [63] & (wr_nz_tsb_cfg_0_4 & tid_dec_4[1])) ;
(t0_e_z [3] & ~(wr_z_tsb_cfg_3_4 & tid_dec_4[0])) |
(data_3 [63] & (wr_z_tsb_cfg_3_4 & tid_dec_4[0])) ;
(t0_e_z [2] & ~(wr_z_tsb_cfg_2_4 & tid_dec_4[0])) |
(data_3 [63] & (wr_z_tsb_cfg_2_4 & tid_dec_4[0])) ;
(t0_e_z [1] & ~(wr_z_tsb_cfg_1_4 & tid_dec_4[0])) |
(data_3 [63] & (wr_z_tsb_cfg_1_4 & tid_dec_4[0])) ;
(t0_e_z [0] & ~(wr_z_tsb_cfg_0_4 & tid_dec_4[0])) |
(data_3 [63] & (wr_z_tsb_cfg_0_4 & tid_dec_4[0])) ;
(t0_e_nz [3] & ~(wr_nz_tsb_cfg_3_4 & tid_dec_4[0])) |
(data_3 [63] & (wr_nz_tsb_cfg_3_4 & tid_dec_4[0])) ;
(t0_e_nz [2] & ~(wr_nz_tsb_cfg_2_4 & tid_dec_4[0])) |
(data_3 [63] & (wr_nz_tsb_cfg_2_4 & tid_dec_4[0])) ;
(t0_e_nz [1] & ~(wr_nz_tsb_cfg_1_4 & tid_dec_4[0])) |
(data_3 [63] & (wr_nz_tsb_cfg_1_4 & tid_dec_4[0])) ;
(t0_e_nz [0] & ~(wr_nz_tsb_cfg_0_4 & tid_dec_4[0])) |
(data_3 [63] & (wr_nz_tsb_cfg_0_4 & tid_dec_4[0])) ;
mmu_asi_ctl_msff_ctl_macro__width_64 hw_tw_e_lat ( // FS:wmr_protect
.scan_in(hw_tw_e_lat_wmr_scanin),
.scan_out(hw_tw_e_lat_wmr_scanout),
assign mmu_hw_tw_enable[7] =
(| {t7_e_z[3:0], t7_e_nz[3:0]});
assign mmu_hw_tw_enable[6] =
(| {t6_e_z[3:0], t6_e_nz[3:0]});
assign mmu_hw_tw_enable[5] =
(| {t5_e_z[3:0], t5_e_nz[3:0]});
assign mmu_hw_tw_enable[4] =
(| {t4_e_z[3:0], t4_e_nz[3:0]});
assign mmu_hw_tw_enable[3] =
(| {t3_e_z[3:0], t3_e_nz[3:0]});
assign mmu_hw_tw_enable[2] =
(| {t2_e_z[3:0], t2_e_nz[3:0]});
assign mmu_hw_tw_enable[1] =
(| {t1_e_z[3:0], t1_e_nz[3:0]});
assign mmu_hw_tw_enable[0] =
(| {t0_e_z[3:0], t0_e_nz[3:0]});
// Mux the enables for ASI read
assign hwtw_enables[7:0] =
({t7_e_z[3:0], t7_e_nz[3:0]} & {8 {rd_tid_dec[7]}}) |
({t6_e_z[3:0], t6_e_nz[3:0]} & {8 {rd_tid_dec[6]}}) |
({t5_e_z[3:0], t5_e_nz[3:0]} & {8 {rd_tid_dec[5]}}) |
({t4_e_z[3:0], t4_e_nz[3:0]} & {8 {rd_tid_dec[4]}}) |
({t3_e_z[3:0], t3_e_nz[3:0]} & {8 {rd_tid_dec[3]}}) |
({t2_e_z[3:0], t2_e_nz[3:0]} & {8 {rd_tid_dec[2]}}) |
({t1_e_z[3:0], t1_e_nz[3:0]} & {8 {rd_tid_dec[1]}}) |
({t0_e_z[3:0], t0_e_nz[3:0]} & {8 {rd_tid_dec[0]}}) ;
(hwtw_enables[7] & z_tsb_cfg_3) |
(hwtw_enables[6] & z_tsb_cfg_2) |
(hwtw_enables[5] & z_tsb_cfg_1) |
(hwtw_enables[4] & z_tsb_cfg_0) |
(hwtw_enables[3] & nz_tsb_cfg_3) |
(hwtw_enables[2] & nz_tsb_cfg_2) |
(hwtw_enables[1] & nz_tsb_cfg_1) |
(hwtw_enables[0] & nz_tsb_cfg_0) ;
mmu_asi_ctl_msff_ctl_macro__width_2 tsb_hwtw_en_lat (
.scan_in(tsb_hwtw_en_lat_scanin),
.scan_out(tsb_hwtw_en_lat_scanout),
// Mux the enables for HW TW read
mmu_asi_ctl_msff_ctl_macro__width_4 htc_mra_addr_lat (
.scan_in(htc_mra_addr_lat_scanin),
.scan_out(htc_mra_addr_lat_scanout),
.din ({htc_mra_addr_in [4:3],
.dout ({htc_mra_addr [4:3],
assign htc_tid_dec[3:0] =
{ htc_mra_addr[4] & htc_mra_addr[3],
htc_mra_addr[4] & ~htc_mra_addr[3],
~htc_mra_addr[4] & htc_mra_addr[3],
~htc_mra_addr[4] & ~htc_mra_addr[3]};
assign htc_enables_1_2[7:0] =
({t7_e_z[3:0], t7_e_nz[3:0]} & {8 {htc_tid_dec[3]}}) |
({t6_e_z[3:0], t6_e_nz[3:0]} & {8 {htc_tid_dec[2]}}) |
({t5_e_z[3:0], t5_e_nz[3:0]} & {8 {htc_tid_dec[1]}}) |
({t4_e_z[3:0], t4_e_nz[3:0]} & {8 {htc_tid_dec[0]}}) ;
assign htc_enables_0_2[7:0] =
({t3_e_z[3:0], t3_e_nz[3:0]} & {8 {htc_tid_dec[3]}}) |
({t2_e_z[3:0], t2_e_nz[3:0]} & {8 {htc_tid_dec[2]}}) |
({t1_e_z[3:0], t1_e_nz[3:0]} & {8 {htc_tid_dec[1]}}) |
({t0_e_z[3:0], t0_e_nz[3:0]} & {8 {htc_tid_dec[0]}}) ;
assign htc_sel_tsb_cfg[3:0] =
{~htc_mra_addr[1] & htc_mra_addr[0],
~htc_mra_addr[1] & ~htc_mra_addr[0],
htc_mra_addr[1] & htc_mra_addr[0],
htc_mra_addr[1] & ~htc_mra_addr[0]};
assign htc_hwtw_en_1_2[1:0] =
(htc_enables_1_2[7:6] & {2 {htc_sel_tsb_cfg[3]}}) |
(htc_enables_1_2[5:4] & {2 {htc_sel_tsb_cfg[2]}}) |
(htc_enables_1_2[3:2] & {2 {htc_sel_tsb_cfg[1]}}) |
(htc_enables_1_2[1:0] & {2 {htc_sel_tsb_cfg[0]}}) ;
assign htc_hwtw_en_0_2[1:0] =
(htc_enables_0_2[7:6] & {2 {htc_sel_tsb_cfg[3]}}) |
(htc_enables_0_2[5:4] & {2 {htc_sel_tsb_cfg[2]}}) |
(htc_enables_0_2[3:2] & {2 {htc_sel_tsb_cfg[1]}}) |
(htc_enables_0_2[1:0] & {2 {htc_sel_tsb_cfg[0]}}) ;
assign asi_tsb_hwtw_enable_1[1:0] =
assign asi_tsb_hwtw_enable_0[1:0] =
//////////////////////////////////////////////////////////////////////////////
// Flop data_access index & valid and send to IFU
asd0_itte_index[6:0] | asd1_itte_index[6:0];
mmu_asi_ctl_msff_ctl_macro__width_7 data_access_index_lat (
.scan_in(data_access_index_lat_scanin),
.scan_out(data_access_index_lat_scanout),
.dout (mmu_index [6:0] ),
//////////////////////////////////////////////////////////////////////////////
mmu_asi_ctl_msff_ctl_macro__width_11 error_inject_lat (
.scan_in(error_inject_lat_scanin),
.scan_out(error_inject_lat_scanout),
.din ({error_inject_enable,
error_inject_mask [7:0]}),
error_enable & error_scau;
error_enable & error_mrau;
assign asi_error_mask[7:0] =
//////////////////////////////////////////////////////////////////////////////
// Tag access power management
mmu_asi_ctl_msff_ctl_macro__width_2 tag_access_tid_0_lat (
.scan_in(tag_access_tid_0_lat_scanin),
.scan_out(tag_access_tid_0_lat_scanout),
.din (tlu_tag_access_tid_0_b [1:0] ),
.dout (tag_access_tid_0 [1:0] ),
mmu_asi_ctl_msff_ctl_macro__width_1 i_tag_access_0_lat (
.scan_in(i_tag_access_0_lat_scanin),
.scan_out(i_tag_access_0_lat_scanout),
.din (tlu_i_tag_access_0_b ),
mmu_asi_ctl_msff_ctl_macro__width_1 d_tag_access_0_lat (
.scan_in(d_tag_access_0_lat_scanin),
.scan_out(d_tag_access_0_lat_scanout),
.din (tlu_d_tag_access_0_b ),
mmu_asi_ctl_msff_ctl_macro__width_2 tag_access_tid_1_lat (
.scan_in(tag_access_tid_1_lat_scanin),
.scan_out(tag_access_tid_1_lat_scanout),
.din (tlu_tag_access_tid_1_b [1:0] ),
.dout (tag_access_tid_1 [1:0] ),
mmu_asi_ctl_msff_ctl_macro__width_1 i_tag_access_1_lat (
.scan_in(i_tag_access_1_lat_scanin),
.scan_out(i_tag_access_1_lat_scanout),
.din (tlu_i_tag_access_1_b ),
mmu_asi_ctl_msff_ctl_macro__width_1 d_tag_access_1_lat (
.scan_in(d_tag_access_1_lat_scanin),
.scan_out(d_tag_access_1_lat_scanout),
.din (tlu_d_tag_access_1_b ),
assign i_tag_access_exc[7:0] =
{(tag_access_tid_1[1:0] == 2'b11) & i_tag_access_1,
(tag_access_tid_1[1:0] == 2'b10) & i_tag_access_1,
(tag_access_tid_1[1:0] == 2'b01) & i_tag_access_1,
(tag_access_tid_1[1:0] == 2'b00) & i_tag_access_1,
(tag_access_tid_0[1:0] == 2'b11) & i_tag_access_0,
(tag_access_tid_0[1:0] == 2'b10) & i_tag_access_0,
(tag_access_tid_0[1:0] == 2'b01) & i_tag_access_0,
(tag_access_tid_0[1:0] == 2'b00) & i_tag_access_0};
assign d_tag_access_exc[7:0] =
{(tag_access_tid_1[1:0] == 2'b11) & d_tag_access_1,
(tag_access_tid_1[1:0] == 2'b10) & d_tag_access_1,
(tag_access_tid_1[1:0] == 2'b01) & d_tag_access_1,
(tag_access_tid_1[1:0] == 2'b00) & d_tag_access_1,
(tag_access_tid_0[1:0] == 2'b11) & d_tag_access_0,
(tag_access_tid_0[1:0] == 2'b10) & d_tag_access_0,
(tag_access_tid_0[1:0] == 2'b01) & d_tag_access_0,
(tag_access_tid_0[1:0] == 2'b00) & d_tag_access_0};
assign asi_i_tag_access_en[7:0] =
a_wr_immu_tag_access[7:0] |
assign asi_d_tag_access_en[7:0] =
a_wr_dmmu_tag_access[7:0] |
//////////////////////////////////////////////////////////////////////////////
// Data in power management
assign asi_i_data_in_en[7:0] =
a_wr_itlb_data_access[7:0] |
assign asi_d_data_in_en[7:0] =
a_wr_dtlb_data_access[7:0] |
//////////////////////////////////////////////////////////////////////////////
// Tablewalk in progress registers
{8 {wr_t_p_c_2}} & wr_tid_dec[7:0];
( write_stp[7:0] & {8 {data_1[0]}}) |
(~write_stp[7:0] & stp[7:0] ) ;
mmu_asi_ctl_msff_ctl_macro__width_8 stp_lat (
.scan_in(stp_lat_scanin),
.scan_out(stp_lat_scanout),
tlu_iht_request[7:0] | tlu_dht_request[7:0];
// Can clear htp when hardware tablewalk fails
// but on successful hardware tablewalk, must wait until the write to the
// TLB is in progress and no longer pending
(rd_dtte_hwtw[7:0] & wrote_dtlb_in[7:0]) |
mmu_i_unauth_access[7:0] |
mmu_i_tsb_miss[7:0] | mmu_d_tsb_miss[7:0] |
mmu_i_tte_outofrange[7:0] | mmu_d_tte_outofrange[7:0] |
mmu_i_eccerr[7:0] | mmu_d_eccerr[7:0];
set_htp[7:0] | (htp[7:0] & ~clr_htp[7:0]);
mmu_asi_ctl_msff_ctl_macro__width_8 htp_lat (
.scan_in(htp_lat_scanin),
.scan_out(htp_lat_scanout),
assign rd_t_p_c_data[63:0] =
{{63 {1'b0}}, | (stp[7:0] & wr_tid_dec[7:0])};
assign rd_t_p_s_data[63:0] =
{{24 {1'b0}}, htp[7:0], {24 {1'b0}}, stp[7:0]};
//////////////////////////////////////////////////////////////////////////////
mmu_asi_ctl_spare_ctl_macro__num_12 spares (
.scan_out(spares_scanout),
supply0 vss; // <- port for ground
supply1 vdd; // <- port for power
assign stg1_en_lat_scanin = scan_in ;
assign stg2_en_lat_scanin = stg1_en_lat_scanout ;
assign stg3_en_lat_scanin = stg2_en_lat_scanout ;
assign stg4_en_lat_scanin = stg3_en_lat_scanout ;
assign mbist_run_lat_scanin = stg4_en_lat_scanout ;
assign mra0_wr_en_lat_scanin = mbist_run_lat_scanout ;
assign mra1_wr_en_lat_scanin = mra0_wr_en_lat_scanout ;
assign scp0_wr_en_lat_scanin = mra1_wr_en_lat_scanout ;
assign scp1_wr_en_lat_scanin = scp0_wr_en_lat_scanout ;
assign mbist_addr_lat_scanin = scp1_wr_en_lat_scanout ;
assign mbist_wdata_lat_scanin = mbist_addr_lat_scanout ;
assign mra0_rd_en_lat_scanin = mbist_wdata_lat_scanout ;
assign mra1_rd_en_lat_scanin = mra0_rd_en_lat_scanout ;
assign scp0_rd_en_lat_scanin = mra1_rd_en_lat_scanout ;
assign scp1_rd_en_lat_scanin = scp0_rd_en_lat_scanout ;
assign mbist_cmpsel_lat_scanin = scp1_rd_en_lat_scanout ;
assign mra0_wr_en_2_lat_scanin = mbist_cmpsel_lat_scanout ;
assign mra1_wr_en_2_lat_scanin = mra0_wr_en_2_lat_scanout ;
assign mra0_rd_en_2_lat_scanin = mra1_wr_en_2_lat_scanout ;
assign mra1_rd_en_2_lat_scanin = mra0_rd_en_2_lat_scanout ;
assign scp0_rd_en_2_lat_scanin = mra1_rd_en_2_lat_scanout ;
assign scp1_rd_en_2_lat_scanin = scp0_rd_en_2_lat_scanout ;
assign mbist_addr_2_lat_scanin = scp1_rd_en_2_lat_scanout ;
assign mbist_cmpsel_2_lat_scanin = mbist_addr_2_lat_scanout ;
assign mbist_compare_data_lat_scanin = mbist_cmpsel_2_lat_scanout;
assign mra0_rd_en_3_lat_scanin = mbist_compare_data_lat_scanout;
assign mra1_rd_en_3_lat_scanin = mra0_rd_en_3_lat_scanout ;
assign scp0_rd_en_3_lat_scanin = mra1_rd_en_3_lat_scanout ;
assign scp1_rd_en_3_lat_scanin = scp0_rd_en_3_lat_scanout ;
assign mra0_rd_en_4_lat_scanin = scp1_rd_en_3_lat_scanout ;
assign mra1_rd_en_4_lat_scanin = mra0_rd_en_4_lat_scanout ;
assign mra0_fail_lat_scanin = mra1_rd_en_4_lat_scanout ;
assign mra1_fail_lat_scanin = mra0_fail_lat_scanout ;
assign scp0_fail_lat_scanin = mra1_fail_lat_scanout ;
assign scp1_fail_lat_scanin = scp0_fail_lat_scanout ;
assign rng_stg1_data_scanin = scp1_fail_lat_scanout ;
assign ctl_1_lat_scanin = rng_stg1_data_scanout ;
assign scp_ctl_lat_scanin = ctl_1_lat_scanout ;
assign rd_scratchpad_4_lat_scanin = scp_ctl_lat_scanout ;
assign req_grant_lat_scanin = rd_scratchpad_4_lat_scanout;
assign mra_addr_lat_scanin = req_grant_lat_scanout ;
assign mra_rd_en_lat_scanin = mra_addr_lat_scanout ;
assign mra_wr_en_lat_scanin = mra_rd_en_lat_scanout ;
assign mra_wr_en_4_lat_scanin = mra_wr_en_lat_scanout ;
assign mra_sel_lat_scanin = mra_wr_en_4_lat_scanout ;
assign stg2_data_lat_scanin = mra_sel_lat_scanout ;
assign stg2_ctl_lat_scanin = stg2_data_lat_scanout ;
assign dae_req_lat_scanin = stg2_ctl_lat_scanout ;
assign check_ecc_lat_scanin = dae_req_lat_scanout ;
assign pmra_to_r4_lat_scanin = check_ecc_lat_scanout ;
assign tid_4_lat_scanin = pmra_to_r4_lat_scanout ;
assign sca_index_lat_scanin = tid_4_lat_scanout ;
assign rng_stg3_scanin = sca_index_lat_scanout ;
assign stg3_ctl_lat_scanin = rng_stg3_scanout ;
assign asi_read_lat_scanin = stg3_ctl_lat_scanout ;
assign rd_tte_lat_scanin = asi_read_lat_scanout ;
assign idata_in_data_access_2_lat_scanin = rd_tte_lat_scanout ;
assign rd_itte_lat_scanin = idata_in_data_access_2_lat_scanout;
assign dtlb_window_used_last_lat_scanin = rd_itte_lat_scanout ;
assign wrote_dtlb_tg1_lat_scanin = dtlb_window_used_last_lat_scanout;
assign wrote_dtlb_tg0_lat_scanin = wrote_dtlb_tg1_lat_scanout;
assign reload_done_tg1_lat_scanin = wrote_dtlb_tg0_lat_scanout;
assign reload_done_tg0_lat_scanin = reload_done_tg1_lat_scanout;
assign dtlb_reload_stall_lat_scanin = reload_done_tg0_lat_scanout;
assign dtlb_reload_lat_scanin = dtlb_reload_stall_lat_scanout;
assign wr_tsb_cfg_lat_scanin = dtlb_reload_lat_scanout ;
assign tsb_hwtw_en_lat_scanin = wr_tsb_cfg_lat_scanout ;
assign htc_mra_addr_lat_scanin = tsb_hwtw_en_lat_scanout ;
assign data_access_index_lat_scanin = htc_mra_addr_lat_scanout ;
assign error_inject_lat_scanin = data_access_index_lat_scanout;
assign tag_access_tid_0_lat_scanin = error_inject_lat_scanout ;
assign i_tag_access_0_lat_scanin = tag_access_tid_0_lat_scanout;
assign d_tag_access_0_lat_scanin = i_tag_access_0_lat_scanout;
assign tag_access_tid_1_lat_scanin = d_tag_access_0_lat_scanout;
assign i_tag_access_1_lat_scanin = tag_access_tid_1_lat_scanout;
assign d_tag_access_1_lat_scanin = i_tag_access_1_lat_scanout;
assign stp_lat_scanin = d_tag_access_1_lat_scanout;
assign htp_lat_scanin = stp_lat_scanout ;
assign spares_scanin = htp_lat_scanout ;
assign scan_out = spares_scanout ;
assign hwtw_config_0_lat_wmr_scanin = wmr_scan_in ;
assign hwtw_config_1_lat_wmr_scanin = hwtw_config_0_lat_wmr_scanout;
assign hwtw_config_2_lat_wmr_scanin = hwtw_config_1_lat_wmr_scanout;
assign hwtw_config_3_lat_wmr_scanin = hwtw_config_2_lat_wmr_scanout;
assign hwtw_config_4_lat_wmr_scanin = hwtw_config_3_lat_wmr_scanout;
assign hwtw_config_5_lat_wmr_scanin = hwtw_config_4_lat_wmr_scanout;
assign hwtw_config_6_lat_wmr_scanin = hwtw_config_5_lat_wmr_scanout;
assign hwtw_config_7_lat_wmr_scanin = hwtw_config_6_lat_wmr_scanout;
assign hw_tw_e_lat_wmr_scanin = hwtw_config_7_lat_wmr_scanout;
assign wmr_scan_out = hw_tw_e_lat_wmr_scanout ;
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_l1clkhdr_ctl_macro (
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_1 (
assign fdin[0:0] = din[0:0];
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_5 (
assign fdin[4:0] = din[4:0];
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_8 (
assign fdin[7:0] = din[7:0];
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_2 (
assign fdin[1:0] = din[1:0];
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_24 (
assign fdin[23:0] = din[23:0];
.so({so[22:0],scan_out}),
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_64 (
assign fdin[63:0] = din[63:0];
.so({so[62:0],scan_out}),
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_15 (
assign fdin[14:0] = din[14:0];
.so({so[13:0],scan_out}),
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_6 (
assign fdin[5:0] = din[5:0];
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_4 (
assign fdin[3:0] = din[3:0];
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_16 (
assign fdin[15:0] = din[15:0];
.so({so[14:0],scan_out}),
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_3 (
assign fdin[2:0] = din[2:0];
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_65 (
assign fdin[64:0] = din[64:0];
.so({so[63:0],scan_out}),
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_25 (
assign fdin[24:0] = din[24:0];
.so({so[23:0],scan_out}),
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_32 (
assign fdin[31:0] = din[31:0];
.so({so[30:0],scan_out}),
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_12 (
assign fdin[11:0] = din[11:0];
.so({so[10:0],scan_out}),
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_7 (
assign fdin[6:0] = din[6:0];
// any PARAMS parms go into naming of macro
module mmu_asi_ctl_msff_ctl_macro__width_11 (
assign fdin[10:0] = din[10:0];
// Description: Spare gate macro for control blocks
// Param num controls the number of times the macro is added
// flops=0 can be used to use only combination spare logic
module mmu_asi_ctl_spare_ctl_macro__num_12 (
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
wire spare5_buf_32x_unused;
wire spare5_nand3_8x_unused;
wire spare5_inv_8x_unused;
wire spare5_aoi22_4x_unused;
wire spare5_buf_8x_unused;
wire spare5_oai22_4x_unused;
wire spare5_inv_16x_unused;
wire spare5_nand2_16x_unused;
wire spare5_nor3_4x_unused;
wire spare5_nand2_8x_unused;
wire spare5_buf_16x_unused;
wire spare5_nor2_16x_unused;
wire spare5_inv_32x_unused;
wire spare6_buf_32x_unused;
wire spare6_nand3_8x_unused;
wire spare6_inv_8x_unused;
wire spare6_aoi22_4x_unused;
wire spare6_buf_8x_unused;
wire spare6_oai22_4x_unused;
wire spare6_inv_16x_unused;
wire spare6_nand2_16x_unused;
wire spare6_nor3_4x_unused;
wire spare6_nand2_8x_unused;
wire spare6_buf_16x_unused;
wire spare6_nor2_16x_unused;
wire spare6_inv_32x_unused;
wire spare7_buf_32x_unused;
wire spare7_nand3_8x_unused;
wire spare7_inv_8x_unused;
wire spare7_aoi22_4x_unused;
wire spare7_buf_8x_unused;
wire spare7_oai22_4x_unused;
wire spare7_inv_16x_unused;
wire spare7_nand2_16x_unused;
wire spare7_nor3_4x_unused;
wire spare7_nand2_8x_unused;
wire spare7_buf_16x_unused;
wire spare7_nor2_16x_unused;
wire spare7_inv_32x_unused;
wire spare8_buf_32x_unused;
wire spare8_nand3_8x_unused;
wire spare8_inv_8x_unused;
wire spare8_aoi22_4x_unused;
wire spare8_buf_8x_unused;
wire spare8_oai22_4x_unused;
wire spare8_inv_16x_unused;
wire spare8_nand2_16x_unused;
wire spare8_nor3_4x_unused;
wire spare8_nand2_8x_unused;
wire spare8_buf_16x_unused;
wire spare8_nor2_16x_unused;
wire spare8_inv_32x_unused;
wire spare9_buf_32x_unused;
wire spare9_nand3_8x_unused;
wire spare9_inv_8x_unused;
wire spare9_aoi22_4x_unused;
wire spare9_buf_8x_unused;
wire spare9_oai22_4x_unused;
wire spare9_inv_16x_unused;
wire spare9_nand2_16x_unused;
wire spare9_nor3_4x_unused;
wire spare9_nand2_8x_unused;
wire spare9_buf_16x_unused;
wire spare9_nor2_16x_unused;
wire spare9_inv_32x_unused;
wire spare10_flop_unused;
wire spare10_buf_32x_unused;
wire spare10_nand3_8x_unused;
wire spare10_inv_8x_unused;
wire spare10_aoi22_4x_unused;
wire spare10_buf_8x_unused;
wire spare10_oai22_4x_unused;
wire spare10_inv_16x_unused;
wire spare10_nand2_16x_unused;
wire spare10_nor3_4x_unused;
wire spare10_nand2_8x_unused;
wire spare10_buf_16x_unused;
wire spare10_nor2_16x_unused;
wire spare10_inv_32x_unused;
wire spare11_flop_unused;
wire spare11_buf_32x_unused;
wire spare11_nand3_8x_unused;
wire spare11_inv_8x_unused;
wire spare11_aoi22_4x_unused;
wire spare11_buf_8x_unused;
wire spare11_oai22_4x_unused;
wire spare11_inv_16x_unused;
wire spare11_nand2_16x_unused;
wire spare11_nor3_4x_unused;
wire spare11_nand2_8x_unused;
wire spare11_buf_16x_unused;
wire spare11_nor2_16x_unused;
wire spare11_inv_32x_unused;
cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
cl_u1_buf_32x spare0_buf_32x (.in(1'b1),
.out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
.out(spare0_nand3_8x_unused));
cl_u1_inv_8x spare0_inv_8x (.in(1'b1),
.out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
.out(spare0_aoi22_4x_unused));
cl_u1_buf_8x spare0_buf_8x (.in(1'b1),
.out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
.out(spare0_oai22_4x_unused));
cl_u1_inv_16x spare0_inv_16x (.in(1'b1),
.out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
.out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
.out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
.out(spare0_nand2_8x_unused));
cl_u1_buf_16x spare0_buf_16x (.in(1'b1),
.out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
.out(spare0_nor2_16x_unused));
cl_u1_inv_32x spare0_inv_32x (.in(1'b1),
.out(spare0_inv_32x_unused));
cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
cl_u1_buf_32x spare1_buf_32x (.in(1'b1),
.out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
.out(spare1_nand3_8x_unused));
cl_u1_inv_8x spare1_inv_8x (.in(1'b1),
.out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
.out(spare1_aoi22_4x_unused));
cl_u1_buf_8x spare1_buf_8x (.in(1'b1),
.out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
.out(spare1_oai22_4x_unused));
cl_u1_inv_16x spare1_inv_16x (.in(1'b1),
.out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
.out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
.out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
.out(spare1_nand2_8x_unused));
cl_u1_buf_16x spare1_buf_16x (.in(1'b1),
.out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
.out(spare1_nor2_16x_unused));
cl_u1_inv_32x spare1_inv_32x (.in(1'b1),
.out(spare1_inv_32x_unused));
cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
cl_u1_buf_32x spare2_buf_32x (.in(1'b1),
.out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
.out(spare2_nand3_8x_unused));
cl_u1_inv_8x spare2_inv_8x (.in(1'b1),
.out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
.out(spare2_aoi22_4x_unused));
cl_u1_buf_8x spare2_buf_8x (.in(1'b1),
.out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
.out(spare2_oai22_4x_unused));
cl_u1_inv_16x spare2_inv_16x (.in(1'b1),
.out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
.out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
.out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
.out(spare2_nand2_8x_unused));
cl_u1_buf_16x spare2_buf_16x (.in(1'b1),
.out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
.out(spare2_nor2_16x_unused));
cl_u1_inv_32x spare2_inv_32x (.in(1'b1),
.out(spare2_inv_32x_unused));
cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
cl_u1_buf_32x spare3_buf_32x (.in(1'b1),
.out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
.out(spare3_nand3_8x_unused));
cl_u1_inv_8x spare3_inv_8x (.in(1'b1),
.out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
.out(spare3_aoi22_4x_unused));
cl_u1_buf_8x spare3_buf_8x (.in(1'b1),
.out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
.out(spare3_oai22_4x_unused));
cl_u1_inv_16x spare3_inv_16x (.in(1'b1),
.out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
.out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
.out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
.out(spare3_nand2_8x_unused));
cl_u1_buf_16x spare3_buf_16x (.in(1'b1),
.out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
.out(spare3_nor2_16x_unused));
cl_u1_inv_32x spare3_inv_32x (.in(1'b1),
.out(spare3_inv_32x_unused));
cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
cl_u1_buf_32x spare4_buf_32x (.in(1'b1),
.out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
.out(spare4_nand3_8x_unused));
cl_u1_inv_8x spare4_inv_8x (.in(1'b1),
.out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
.out(spare4_aoi22_4x_unused));
cl_u1_buf_8x spare4_buf_8x (.in(1'b1),
.out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
.out(spare4_oai22_4x_unused));
cl_u1_inv_16x spare4_inv_16x (.in(1'b1),
.out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
.out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
.out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
.out(spare4_nand2_8x_unused));
cl_u1_buf_16x spare4_buf_16x (.in(1'b1),
.out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
.out(spare4_nor2_16x_unused));
cl_u1_inv_32x spare4_inv_32x (.in(1'b1),
.out(spare4_inv_32x_unused));
cl_sc1_msff_8x spare5_flop (.l1clk(l1clk),
cl_u1_buf_32x spare5_buf_32x (.in(1'b1),
.out(spare5_buf_32x_unused));
cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1),
.out(spare5_nand3_8x_unused));
cl_u1_inv_8x spare5_inv_8x (.in(1'b1),
.out(spare5_inv_8x_unused));
cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1),
.out(spare5_aoi22_4x_unused));
cl_u1_buf_8x spare5_buf_8x (.in(1'b1),
.out(spare5_buf_8x_unused));
cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1),
.out(spare5_oai22_4x_unused));
cl_u1_inv_16x spare5_inv_16x (.in(1'b1),
.out(spare5_inv_16x_unused));
cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1),
.out(spare5_nand2_16x_unused));
cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0),
.out(spare5_nor3_4x_unused));
cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1),
.out(spare5_nand2_8x_unused));
cl_u1_buf_16x spare5_buf_16x (.in(1'b1),
.out(spare5_buf_16x_unused));
cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0),
.out(spare5_nor2_16x_unused));
cl_u1_inv_32x spare5_inv_32x (.in(1'b1),
.out(spare5_inv_32x_unused));
cl_sc1_msff_8x spare6_flop (.l1clk(l1clk),
cl_u1_buf_32x spare6_buf_32x (.in(1'b1),
.out(spare6_buf_32x_unused));
cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1),
.out(spare6_nand3_8x_unused));
cl_u1_inv_8x spare6_inv_8x (.in(1'b1),
.out(spare6_inv_8x_unused));
cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1),
.out(spare6_aoi22_4x_unused));
cl_u1_buf_8x spare6_buf_8x (.in(1'b1),
.out(spare6_buf_8x_unused));
cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1),
.out(spare6_oai22_4x_unused));
cl_u1_inv_16x spare6_inv_16x (.in(1'b1),
.out(spare6_inv_16x_unused));
cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1),
.out(spare6_nand2_16x_unused));
cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0),
.out(spare6_nor3_4x_unused));
cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1),
.out(spare6_nand2_8x_unused));
cl_u1_buf_16x spare6_buf_16x (.in(1'b1),
.out(spare6_buf_16x_unused));
cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0),
.out(spare6_nor2_16x_unused));
cl_u1_inv_32x spare6_inv_32x (.in(1'b1),
.out(spare6_inv_32x_unused));
cl_sc1_msff_8x spare7_flop (.l1clk(l1clk),
cl_u1_buf_32x spare7_buf_32x (.in(1'b1),
.out(spare7_buf_32x_unused));
cl_u1_nand3_8x spare7_nand3_8x (.in0(1'b1),
.out(spare7_nand3_8x_unused));
cl_u1_inv_8x spare7_inv_8x (.in(1'b1),
.out(spare7_inv_8x_unused));
cl_u1_aoi22_4x spare7_aoi22_4x (.in00(1'b1),
.out(spare7_aoi22_4x_unused));
cl_u1_buf_8x spare7_buf_8x (.in(1'b1),
.out(spare7_buf_8x_unused));
cl_u1_oai22_4x spare7_oai22_4x (.in00(1'b1),
.out(spare7_oai22_4x_unused));
cl_u1_inv_16x spare7_inv_16x (.in(1'b1),
.out(spare7_inv_16x_unused));
cl_u1_nand2_16x spare7_nand2_16x (.in0(1'b1),
.out(spare7_nand2_16x_unused));
cl_u1_nor3_4x spare7_nor3_4x (.in0(1'b0),
.out(spare7_nor3_4x_unused));
cl_u1_nand2_8x spare7_nand2_8x (.in0(1'b1),
.out(spare7_nand2_8x_unused));
cl_u1_buf_16x spare7_buf_16x (.in(1'b1),
.out(spare7_buf_16x_unused));
cl_u1_nor2_16x spare7_nor2_16x (.in0(1'b0),
.out(spare7_nor2_16x_unused));
cl_u1_inv_32x spare7_inv_32x (.in(1'b1),
.out(spare7_inv_32x_unused));
cl_sc1_msff_8x spare8_flop (.l1clk(l1clk),
cl_u1_buf_32x spare8_buf_32x (.in(1'b1),
.out(spare8_buf_32x_unused));
cl_u1_nand3_8x spare8_nand3_8x (.in0(1'b1),
.out(spare8_nand3_8x_unused));
cl_u1_inv_8x spare8_inv_8x (.in(1'b1),
.out(spare8_inv_8x_unused));
cl_u1_aoi22_4x spare8_aoi22_4x (.in00(1'b1),
.out(spare8_aoi22_4x_unused));
cl_u1_buf_8x spare8_buf_8x (.in(1'b1),
.out(spare8_buf_8x_unused));
cl_u1_oai22_4x spare8_oai22_4x (.in00(1'b1),
.out(spare8_oai22_4x_unused));
cl_u1_inv_16x spare8_inv_16x (.in(1'b1),
.out(spare8_inv_16x_unused));
cl_u1_nand2_16x spare8_nand2_16x (.in0(1'b1),
.out(spare8_nand2_16x_unused));
cl_u1_nor3_4x spare8_nor3_4x (.in0(1'b0),
.out(spare8_nor3_4x_unused));
cl_u1_nand2_8x spare8_nand2_8x (.in0(1'b1),
.out(spare8_nand2_8x_unused));
cl_u1_buf_16x spare8_buf_16x (.in(1'b1),
.out(spare8_buf_16x_unused));
cl_u1_nor2_16x spare8_nor2_16x (.in0(1'b0),
.out(spare8_nor2_16x_unused));
cl_u1_inv_32x spare8_inv_32x (.in(1'b1),
.out(spare8_inv_32x_unused));
cl_sc1_msff_8x spare9_flop (.l1clk(l1clk),
cl_u1_buf_32x spare9_buf_32x (.in(1'b1),
.out(spare9_buf_32x_unused));
cl_u1_nand3_8x spare9_nand3_8x (.in0(1'b1),
.out(spare9_nand3_8x_unused));
cl_u1_inv_8x spare9_inv_8x (.in(1'b1),
.out(spare9_inv_8x_unused));
cl_u1_aoi22_4x spare9_aoi22_4x (.in00(1'b1),
.out(spare9_aoi22_4x_unused));
cl_u1_buf_8x spare9_buf_8x (.in(1'b1),
.out(spare9_buf_8x_unused));
cl_u1_oai22_4x spare9_oai22_4x (.in00(1'b1),
.out(spare9_oai22_4x_unused));
cl_u1_inv_16x spare9_inv_16x (.in(1'b1),
.out(spare9_inv_16x_unused));
cl_u1_nand2_16x spare9_nand2_16x (.in0(1'b1),
.out(spare9_nand2_16x_unused));
cl_u1_nor3_4x spare9_nor3_4x (.in0(1'b0),
.out(spare9_nor3_4x_unused));
cl_u1_nand2_8x spare9_nand2_8x (.in0(1'b1),
.out(spare9_nand2_8x_unused));
cl_u1_buf_16x spare9_buf_16x (.in(1'b1),
.out(spare9_buf_16x_unused));
cl_u1_nor2_16x spare9_nor2_16x (.in0(1'b0),
.out(spare9_nor2_16x_unused));
cl_u1_inv_32x spare9_inv_32x (.in(1'b1),
.out(spare9_inv_32x_unused));
cl_sc1_msff_8x spare10_flop (.l1clk(l1clk),
.q(spare10_flop_unused));
cl_u1_buf_32x spare10_buf_32x (.in(1'b1),
.out(spare10_buf_32x_unused));
cl_u1_nand3_8x spare10_nand3_8x (.in0(1'b1),
.out(spare10_nand3_8x_unused));
cl_u1_inv_8x spare10_inv_8x (.in(1'b1),
.out(spare10_inv_8x_unused));
cl_u1_aoi22_4x spare10_aoi22_4x (.in00(1'b1),
.out(spare10_aoi22_4x_unused));
cl_u1_buf_8x spare10_buf_8x (.in(1'b1),
.out(spare10_buf_8x_unused));
cl_u1_oai22_4x spare10_oai22_4x (.in00(1'b1),
.out(spare10_oai22_4x_unused));
cl_u1_inv_16x spare10_inv_16x (.in(1'b1),
.out(spare10_inv_16x_unused));
cl_u1_nand2_16x spare10_nand2_16x (.in0(1'b1),
.out(spare10_nand2_16x_unused));
cl_u1_nor3_4x spare10_nor3_4x (.in0(1'b0),
.out(spare10_nor3_4x_unused));
cl_u1_nand2_8x spare10_nand2_8x (.in0(1'b1),
.out(spare10_nand2_8x_unused));
cl_u1_buf_16x spare10_buf_16x (.in(1'b1),
.out(spare10_buf_16x_unused));
cl_u1_nor2_16x spare10_nor2_16x (.in0(1'b0),
.out(spare10_nor2_16x_unused));
cl_u1_inv_32x spare10_inv_32x (.in(1'b1),
.out(spare10_inv_32x_unused));
cl_sc1_msff_8x spare11_flop (.l1clk(l1clk),
.q(spare11_flop_unused));
cl_u1_buf_32x spare11_buf_32x (.in(1'b1),
.out(spare11_buf_32x_unused));
cl_u1_nand3_8x spare11_nand3_8x (.in0(1'b1),
.out(spare11_nand3_8x_unused));
cl_u1_inv_8x spare11_inv_8x (.in(1'b1),
.out(spare11_inv_8x_unused));
cl_u1_aoi22_4x spare11_aoi22_4x (.in00(1'b1),
.out(spare11_aoi22_4x_unused));
cl_u1_buf_8x spare11_buf_8x (.in(1'b1),
.out(spare11_buf_8x_unused));
cl_u1_oai22_4x spare11_oai22_4x (.in00(1'b1),
.out(spare11_oai22_4x_unused));
cl_u1_inv_16x spare11_inv_16x (.in(1'b1),
.out(spare11_inv_16x_unused));
cl_u1_nand2_16x spare11_nand2_16x (.in0(1'b1),
.out(spare11_nand2_16x_unused));
cl_u1_nor3_4x spare11_nor3_4x (.in0(1'b0),
.out(spare11_nor3_4x_unused));
cl_u1_nand2_8x spare11_nand2_8x (.in0(1'b1),
.out(spare11_nand2_8x_unused));
cl_u1_buf_16x spare11_buf_16x (.in(1'b1),
.out(spare11_buf_16x_unused));
cl_u1_nor2_16x spare11_nor2_16x (.in0(1'b0),
.out(spare11_nor2_16x_unused));
cl_u1_inv_32x spare11_inv_32x (.in(1'b1),
.out(spare11_inv_32x_unused));