// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: pmu_pdp_dp.v
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pdp_asi_ctlin_to_pctl_15_8,
pdp_asi_ctlin_to_pctl_4_0,
wire [7:0] pdp_pich_wrapa;
wire [7:0] pdp_picl_wrapa;
wire [7:0] pdp_pich_wrapb;
wire [7:0] pdp_picl_wrapb;
wire [63:0] pdp_pic_data;
wire [63:0] pmu_rngl_cdbus_nobuf;
input tcu_pce_ov; // scan signals
input [63:0] in_rngl_cdbus; // ASI ring data input
input [7:0] pct_rd_pic; // ASI read of PIC (bit 7 == read PIC for tid 7)
input pct_rd_a_pic; // ASI read of any PIC
input pct_rd_pic_pcr; // ASI read of PIC or PCR (select PIC or PCR)
input pct_bypass_asi; // Flow this node's ASI data to the output
input [31:0] pct_pcr_data; // PCR data on ASI read
input pct_exception; // If a privileged exception on an ASR read or write to PIC or PCR
input [7:0] pct_pic_clken; // Clock enables for PIC
input pct_pic07_w2_clken; // Clock enable for pic07_w2 flop
input [7:0] pct_wr_pic_w2; // Write corresponding PICH/L from ASI (bit 7 == write PIC7)
input [6:0] pct_incr_pic_w1; // increment PIC (PICL is enabled for counting) W+1 cycle (mux prior to adding)
input pct_incr_asi_w1; // Select new ASI value to increment to deal with simultaneous ASI write and increment
input [3:0] pct_pich07_add_w2; // Add value for pich
input [3:0] pct_picl07_add_w2; // Add value for picl
input pmu_asi_clken; // Gate ASI ring flops
output [63:0] pmu_rngl_cdbus; // ASI ring data out
output [31:0] pdp_asi_din_to_pctl; // for PCR writes
output [7:0] pdp_asi_ctlin_to_pctl_15_8; // Bits 63:56 of registered data from PDP (save 8 flop bits)
output [4:0] pdp_asi_ctlin_to_pctl_4_0; // Bits 63:48 of registered data from PDP (save 5 flop bits)
// Carry-out bits for PCR of each counter
output pdp_pich_cout07; // carry-outs of incrementors, to set OV bits in PCR's
// Wrap indicators for trap generation
output [7:0] pdp_pich_wrap; // If counter within -16..-1
output [7:0] pdp_picl_wrap; // If counter within -16..-1
//assign pce_ov = tcu_pce_ov;
//assign stop = tcu_clk_stop;
//assign siclk = spc_aclk;
//assign soclk = spc_bclk;
//assign se = tcu_scan_en;
pmu_pdp_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0 (
.din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
.dout({se,pce_ov,siclk,soclk})
// First put in the ASI staging reg, bit 64 is flopped in ctl
pmu_pdp_dp_msff_macro__stack_64c__width_64 asi_din (
.scan_in(asi_din_scanin),
.scan_out(asi_din_scanout),
.en ( pmu_asi_clken ), // powerdown pin
.din( in_rngl_cdbus[63:0]),
.dout( pdp_asi_din[63:0]),
assign pdp_asi_din_to_pctl[31:0] = pdp_asi_din[31:0]; // bus to pctl for PCR writes
assign pdp_asi_ctlin_to_pctl_15_8[7:0] = pdp_asi_din[63:56];// Bits 63:56 of registered data from PDP (save 8 flop bits)
assign pdp_asi_ctlin_to_pctl_4_0[4:0] = pdp_asi_din[52:48];// Bits 52:48 of registered data from PDP (save 5 flop bits)
// There are 8, 1 for each thread
// split the 64 bit 3-input mux to two 32 bit ones
// and use AND to zero out the counter values
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic0 (
.en ( pct_pic_clken[0] ), // powerdown pin
.din0( pdp_asi_din[63:0] ),
.din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
.sel0( pct_wr_pic_w2[0] ),
.dout( {pich0[31:0],picl0[31:0]}),
pmu_pdp_dp_cmp_macro__width_16 pic0hca (
.dout(pdp_pich_wrapa[0]));
pmu_pdp_dp_cmp_macro__width_16 pic0lca (
.dout(pdp_picl_wrapa[0]));
pmu_pdp_dp_cmp_macro__width_12 pic0hcb (
.dout(pdp_pich_wrapb[0]));
pmu_pdp_dp_cmp_macro__width_12 pic0lcb (
.dout(pdp_picl_wrapb[0]));
// the ANDing is done for all 8 threads after PIC7
//and_macro pich0wrap (width=2, ports=2) (
// .din0 ({pdp_pich_wrapa[0],pdp_picl_wrapa[0]}),
// .din1 ({pdp_pich_wrapb[0],pdp_picl_wrapb[0]}),
// .dout ({pdp_pich_wrap[0], pdp_picl_wrap[0]});
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic1 (
.en ( pct_pic_clken[1] ), // powerdown pin
.din0( pdp_asi_din[63:0] ),
.din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
.sel0( pct_wr_pic_w2[1] ),
.dout( {pich1[31:0],picl1[31:0]}),
pmu_pdp_dp_cmp_macro__width_16 pic1hca (
.dout(pdp_pich_wrapa[1]));
pmu_pdp_dp_cmp_macro__width_16 pic1lca (
.dout(pdp_picl_wrapa[1]));
pmu_pdp_dp_cmp_macro__width_12 pic1hcb (
.dout(pdp_pich_wrapb[1]));
pmu_pdp_dp_cmp_macro__width_12 pic1lcb (
.dout(pdp_picl_wrapb[1]));
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic2 (
.en ( pct_pic_clken[2] ), // powerdown pin
.din0( pdp_asi_din[63:0] ),
.din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
.sel0( pct_wr_pic_w2[2] ),
.dout( {pich2[31:0],picl2[31:0]}),
pmu_pdp_dp_cmp_macro__width_16 pic2hca (
.dout(pdp_pich_wrapa[2]));
pmu_pdp_dp_cmp_macro__width_16 pic2lca (
.dout(pdp_picl_wrapa[2]));
pmu_pdp_dp_cmp_macro__width_12 pic2hcb (
.dout(pdp_pich_wrapb[2]));
pmu_pdp_dp_cmp_macro__width_12 pic2lcb (
.dout(pdp_picl_wrapb[2]));
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic3 (
.en ( pct_pic_clken[3] ), // powerdown pin
.din0( pdp_asi_din[63:0] ),
.din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
.sel0( pct_wr_pic_w2[3] ),
.dout( {pich3[31:0],picl3[31:0]}),
pmu_pdp_dp_cmp_macro__width_16 pic3hca (
.dout(pdp_pich_wrapa[3]));
pmu_pdp_dp_cmp_macro__width_16 pic3lca (
.dout(pdp_picl_wrapa[3]));
pmu_pdp_dp_cmp_macro__width_12 pic3hcb (
.dout(pdp_pich_wrapb[3]));
pmu_pdp_dp_cmp_macro__width_12 pic3lcb (
.dout(pdp_picl_wrapb[3]));
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic4 (
.en ( pct_pic_clken[4] ), // powerdown pin
.din0( pdp_asi_din[63:0] ),
.din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
.sel0( pct_wr_pic_w2[4] ),
.dout( {pich4[31:0],picl4[31:0]}),
pmu_pdp_dp_cmp_macro__width_16 pic4hca (
.dout(pdp_pich_wrapa[4]));
pmu_pdp_dp_cmp_macro__width_16 pic4lca (
.dout(pdp_picl_wrapa[4]));
pmu_pdp_dp_cmp_macro__width_12 pic4hcb (
.dout(pdp_pich_wrapb[4]));
pmu_pdp_dp_cmp_macro__width_12 pic4lcb (
.dout(pdp_picl_wrapb[4]));
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic5 (
.en ( pct_pic_clken[5] ), // powerdown pin
.din0( pdp_asi_din[63:0] ),
.din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
.sel0( pct_wr_pic_w2[5] ),
.dout( {pich5[31:0],picl5[31:0]}),
pmu_pdp_dp_cmp_macro__width_16 pic5hca (
.dout(pdp_pich_wrapa[5]));
pmu_pdp_dp_cmp_macro__width_16 pic5lca (
.dout(pdp_picl_wrapa[5]));
pmu_pdp_dp_cmp_macro__width_12 pic5hcb (
.dout(pdp_pich_wrapb[5]));
pmu_pdp_dp_cmp_macro__width_12 pic5lcb (
.dout(pdp_picl_wrapb[5]));
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic6 (
.en ( pct_pic_clken[6] ), // powerdown pin
.din0( pdp_asi_din[63:0] ),
.din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
.sel0( pct_wr_pic_w2[6] ),
.dout( {pich6[31:0],picl6[31:0]}),
pmu_pdp_dp_cmp_macro__width_16 pic6hca (
.dout(pdp_pich_wrapa[6]));
pmu_pdp_dp_cmp_macro__width_16 pic6lca (
.dout(pdp_picl_wrapa[6]));
pmu_pdp_dp_cmp_macro__width_12 pic6hcb (
.dout(pdp_pich_wrapb[6]));
pmu_pdp_dp_cmp_macro__width_12 pic6lcb (
.dout(pdp_picl_wrapb[6]));
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic7 (
.en ( pct_pic_clken[7] ), // powerdown pin
.din0( pdp_asi_din[63:0] ),
.din1( {pich07_incr[31:0],picl07_incr[31:0]} ),
.sel0( pct_wr_pic_w2[7] ),
.dout( {pich7[31:0],picl7[31:0]}),
pmu_pdp_dp_cmp_macro__width_16 pic7hca (
.dout(pdp_pich_wrapa[7]));
pmu_pdp_dp_cmp_macro__width_16 pic7lca (
.dout(pdp_picl_wrapa[7]));
pmu_pdp_dp_cmp_macro__width_12 pic7hcb (
.dout(pdp_pich_wrapb[7]));
pmu_pdp_dp_cmp_macro__width_12 pic7lcb (
.dout(pdp_picl_wrapb[7]));
pmu_pdp_dp_and_macro__ports_2__width_16 pich0wrap (
.din0 ({pdp_pich_wrapa[7:0],pdp_picl_wrapa[7:0]}),
.din1 ({pdp_pich_wrapb[7:0],pdp_picl_wrapb[7:0]}),
.dout ({pdp_pich_wrap[7:0], pdp_picl_wrap[7:0]}));
// Mux PIC's 0-7 together to share one incrementor & adder
// Mux in W1 cycle, increment in W2
pmu_pdp_dp_mux_macro__mux_aope__ports_8__width_64 pic07_mux (
.din0({pich0[31:0], picl0[31:0]}),
.din1({pich1[31:0], picl1[31:0]}),
.din2({pich2[31:0], picl2[31:0]}),
.din3({pich3[31:0], picl3[31:0]}),
.din4({pich4[31:0], picl4[31:0]}),
.din5({pich5[31:0], picl5[31:0]}),
.din6({pich6[31:0], picl6[31:0]}),
.din7({pich7[31:0], picl7[31:0]}),
.sel0(pct_incr_pic_w1[0]),
.sel1(pct_incr_pic_w1[1]),
.sel2(pct_incr_pic_w1[2]),
.sel3(pct_incr_pic_w1[3]),
.sel4(pct_incr_pic_w1[4]),
.sel5(pct_incr_pic_w1[5]),
.sel6(pct_incr_pic_w1[6]),
// .sel7(pct_incr_pic_w1[7]), // pct_incr_pic_w1 is guaranteed to be one-hot
.dout({pich07_w1[31:0], picl07_w1[31:0]}));
// all 8 threads sharing two comparators
// not practical, as wrap must be matched with tid in the ctl logic
//cmp_macro pic07hc (width=28) (
// .din0(pich07_w1[31:4]),
// .dout(pdp_pich_wrap));
//cmp_macro pic07lc (width=28) (
// .din0(pich07_w1[31:4]),
// .dout(pdp_picl_wrap));
// send these two wrap signals to the ctl logic and qualify with pct_incr_pic_w1
pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 pic07_w2 (
.scan_in(pic07_w2_scanin),
.scan_out(pic07_w2_scanout),
.en ( pct_pic07_w2_clken ), // powerdown pin
.din0( pdp_asi_din[63:0]),
.din1( {pich07_w1[31:0], picl07_w1[31:0]} ),
.sel0( pct_incr_asi_w1 ),
.dout( {pich07_w2[31:0], picl07_w2[31:0]} ),
// PICH incrementor for PIC's 0-7
pmu_pdp_dp_cla_macro__width_32 pich07_cla (
.din0({28'b0, pct_pich07_add_w2[3:0]}),
.dout(pich07_incr[31:0]),
pmu_pdp_dp_cla_macro__width_32 picl07_cla (
.din0({28'b0, pct_picl07_add_w2[3:0]}),
.dout(picl07_incr[31:0]),
// 8:1 mux for ASR reads to mux between PICs
pmu_pdp_dp_mux_macro__mux_aonpe__ports_8__width_64 pic_mux (
.din0({pich0[31:0],picl0[31:0]}),
.din1({pich1[31:0],picl1[31:0]}),
.din2({pich2[31:0],picl2[31:0]}),
.din3({pich3[31:0],picl3[31:0]}),
.din4({pich4[31:0],picl4[31:0]}),
.din5({pich5[31:0],picl5[31:0]}),
.din6({pich6[31:0],picl6[31:0]}),
.din7({pich7[31:0],picl7[31:0]}),
.dout(pdp_pic_data[63:0]));
pmu_pdp_dp_mux_macro__mux_aope__ports_2__width_64 picpcr_mux (
.din0(pdp_pic_data[63:0]),
.din1({32'b0, pct_pcr_data[31:0]}),
.dout(picpcr_data[63:0]));
pmu_pdp_dp_msff_macro__mux_aope__ports_3__stack_64c__width_64 asi_dout (
.scan_in(asi_dout_scanin),
.scan_out(asi_dout_scanout),
.en ( pmu_asi_clken ), // powerdown pin
.din0( pdp_asi_din[63:0]),
.din1( picpcr_data[63:0]),
.din2({pdp_asi_din[63],1'b1,pdp_asi_din[61:56],6'b0,pct_exception,1'b0,pdp_asi_din[47:0]}),
.dout( pmu_rngl_cdbus_nobuf[63:0]),
// Add buffer to drive FGU since aope muxes can't drive big loads well...
pmu_pdp_dp_buff_macro__dbuff_32x__rep_1__stack_64c__width_64 rngl_out_buf (
.din (pmu_rngl_cdbus_nobuf[63:0]),
.dout(pmu_rngl_cdbus[63:0]));
assign asi_din_scanin = scan_in ;
assign pic0_scanin = asi_din_scanout ;
assign pic1_scanin = pic0_scanout ;
assign pic2_scanin = pic1_scanout ;
assign pic3_scanin = pic2_scanout ;
assign pic4_scanin = pic3_scanout ;
assign pic5_scanin = pic4_scanout ;
assign pic6_scanin = pic5_scanout ;
assign pic7_scanin = pic6_scanout ;
assign pic07_w2_scanin = pic7_scanout ;
assign asi_dout_scanin = pic07_w2_scanout ;
assign scan_out = asi_dout_scanout ;
module pmu_pdp_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
// any PARAMS parms go into naming of macro
module pmu_pdp_dp_msff_macro__stack_64c__width_64 (
.so({so[62:0],scan_out}),
// any PARAMS parms go into naming of macro
module pmu_pdp_dp_msff_macro__mux_aope__ports_2__stack_64c__width_64 (
.so({so[62:0],scan_out}),
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module pmu_pdp_dp_cmp_macro__width_16 (
// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
module pmu_pdp_dp_cmp_macro__width_12 (
// and macro for ports = 2,3,4
module pmu_pdp_dp_and_macro__ports_2__width_16 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module pmu_pdp_dp_mux_macro__mux_aope__ports_8__width_64 (
module pmu_pdp_dp_cla_macro__width_32 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module pmu_pdp_dp_mux_macro__mux_aonpe__ports_8__width_64 (
cl_dp1_muxbuff8_8x c0_0 (
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module pmu_pdp_dp_mux_macro__mux_aope__ports_2__width_64 (
// any PARAMS parms go into naming of macro
module pmu_pdp_dp_msff_macro__mux_aope__ports_3__stack_64c__width_64 (
.so({so[62:0],scan_out}),
module pmu_pdp_dp_buff_macro__dbuff_32x__rep_1__stack_64c__width_64 (