// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: spc_msf0_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// ========== Copyright Header End ============================================
efu_spc_fuse_ixfer_en_buf,
efu_spc_fuse_dxfer_en_buf,
spc_efu_fuse_ixfer_en_buf,
spc_efu_fuse_dxfer_en_buf,
wire cmp_slow_sync_en_ff;
wire [7:0] tlu_core_running_status_rep0;
wire tlu_ss_complete_rep0;
wire tlu_hardstop_request_rep0;
wire tlu_softstop_request_rep0;
wire tlu_trigger_pulse_rep0;
wire [1:0] tlu_dbg_instr_cmt_grp0_rep0;
wire [1:0] tlu_dbg_instr_cmt_grp1_rep0;
wire tcu_ss_request_rep0;
wire slow_cmp_sync_en_ff;
wire efu_spc_fuse_data_bufin;
wire efu_spc_fuse_ixfer_en_bufin;
wire efu_spc_fuse_dxfer_en_bufin;
wire efu_spc_fuse_iclr_bufin;
wire efu_spc_fuse_dclr_bufin;
wire lb_lbist_running_n1;
wire lb_efu_spc_fuse_data;
wire lb_efu_spc_fuse_ixfer_en;
wire lb_efu_spc_fuse_dxfer_en;
wire lb_efu_spc_fuse_iclr;
wire lb_efu_spc_fuse_dclr;
wire ncu_cmp_tick_enable_rep0;
wire [7:0] tcu_core_running_rep0;
wire ncu_wmr_vec_mask_rep0;
wire tcu_mbist_user_mode_rep0;
wire tcu_mbist_bisi_en_rep0;
wire [2:0] tcu_shscanid_rep0;
wire tcu_shscan_clk_stop_rep0;
input tcu_se_scancollar_out;
// Core inputs before the MSFF
input ncu_cmp_tick_enable;
input tcu_mbist_user_mode;
input [7:0] tcu_core_running;
input tcu_shscan_clk_stop;
input [2:0] tcu_shscanid;
input efu_spc_fuse_ixfer_en;
input efu_spc_fuse_dxfer_en;
output spc_efu_fuse_ddata;
output spc_efu_fuse_idata;
output spc_efu_fuse_ixfer_en;
output spc_efu_fuse_dxfer_en;
output efu_spc_fuse_data_buf;
output efu_spc_fuse_ixfer_en_buf;
output efu_spc_fuse_dxfer_en_buf;
output efu_spc_fuse_iclr_buf;
output efu_spc_fuse_dclr_buf;
input spc_efu_fuse_ddata_buf;
input spc_efu_fuse_idata_buf;
input spc_efu_fuse_ixfer_en_buf;
input spc_efu_fuse_dxfer_en_buf;
// Core outputs before the MSFF
input [7:0] tlu_core_running_status;
input tlu_hardstop_request;
input tlu_softstop_request;
input [1:0] tlu_dbg_instr_cmt_grp0;
input [1:0] tlu_dbg_instr_cmt_grp1;
// Core inputs after the MSFF
output msf0_cmp_tick_enable;
output msf0_wmr_vec_mask;
output [7:0] msf0_core_running;
output msf0_shscan_clk_stop;
output [2:0] msf0_shscanid;
output msf0_mbist_user_mode_ff;
output msf0_mbist_bisi_en_ff;
output msf0_atpg_mode_buf;
// Core outputs after the MSFF
output [7:0] spc_core_running_status;
output spc_hardstop_request;
output spc_softstop_request;
output spc_trigger_pulse;
output [1:0] spc_dbg_instr_cmt_grp0;
output [1:0] spc_dbg_instr_cmt_grp1;
input [2:0] power_throttle;
output [2:0] power_throttle_buf;
//////////////////////////////////////////////////////////////////////
assign pce_ov = tcu_pce_ov;
//////////////////////////////////////////////////////////////////////
spc_msf0_dpmsff_macro__stack_10r__width_8 bank0_lat (
.scan_in(bank0_lat_scanin),
.scan_out(bank0_lat_scanout),
.en (cmp_slow_sync_en_ff),
.din (tlu_core_running_status [7:0] ),
.dout (tlu_core_running_status_rep0 [7:0] ),
spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_8 bank0_rep (
.din(tlu_core_running_status_rep0[7:0]),
.dout(spc_core_running_status[7:0])
//inv_macro bank1_inv (width=1) (
// .din(lb_lbist_running),
// .dout(lb_lbist_running_n)
//buff_macro bank1_rep0 (width=3,stack=none,dbuff=16x,rep=1) (
// .din (power_throttle[2:0]),
// .dout (power_throttle_bufin[2:0])
//and_macro bank1_and (width=3) (
// .din0 (power_throttle_bufin[2:0]),
// .din1 ({3 {lb_lbist_running_n}}),
// .dout (lb_power_throttle[2:0])
spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_11 bank1_rep1 (
.din ({tlu_ss_complete_rep0 ,
tlu_hardstop_request_rep0 ,
tlu_softstop_request_rep0 ,
tlu_dbg_instr_cmt_grp0_rep0 [1:0],
tlu_dbg_instr_cmt_grp1_rep0 [1:0]}),
.dout ({spc_ss_complete ,
power_throttle_buf[2:0] ,
spc_dbg_instr_cmt_grp0 [1:0],
spc_dbg_instr_cmt_grp1 [1:0]})
spc_msf0_dpmsff_macro__stack_8r__width_8 bank1_lat (
.scan_in(bank1_lat_scanin),
.scan_out(bank1_lat_scanout),
tlu_dbg_instr_cmt_grp0 [1:0],
tlu_dbg_instr_cmt_grp1 [1:0]}),
.dout ({tlu_ss_complete_rep0 ,
tlu_hardstop_request_rep0 ,
tlu_softstop_request_rep0 ,
tlu_dbg_instr_cmt_grp0_rep0 [1:0],
tlu_dbg_instr_cmt_grp1_rep0 [1:0]}),
spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_1 bank2_rep1 (
.dout (tcu_ss_request_rep0 )
spc_msf0_dpmsff_macro__stack_8r__width_3 bank2_lat (
.scan_in(bank2_lat_scanin),
.scan_out(bank2_lat_scanout),
.se ( tcu_se_scancollar_out ),
.din ({slow_cmp_sync_en ,
.dout ({slow_cmp_sync_en_ff ,
spc_msf0_dpbuff_macro__dbuff_16x__rep_1__stack_none__width_5 bank3_rep0 (
.din ({efu_spc_fuse_data,
.dout ({efu_spc_fuse_data_bufin,
efu_spc_fuse_ixfer_en_bufin,
efu_spc_fuse_dxfer_en_bufin,
efu_spc_fuse_dclr_bufin})
spc_msf0_dpinv_macro__width_1 bank3_inv (
.dout(lb_lbist_running_n1)
spc_msf0_dpand_macro__width_5 bank3_and (
.din0 ({efu_spc_fuse_data_bufin,
efu_spc_fuse_ixfer_en_bufin,
efu_spc_fuse_dxfer_en_bufin,
efu_spc_fuse_dclr_bufin}),
.din1 ({5 {lb_lbist_running_n1}}),
.dout ({lb_efu_spc_fuse_data,
lb_efu_spc_fuse_ixfer_en,
lb_efu_spc_fuse_dxfer_en,
spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_19 bank3_rep1 (
.din ({ncu_cmp_tick_enable ,
lb_efu_spc_fuse_ixfer_en,
lb_efu_spc_fuse_dxfer_en,
spc_efu_fuse_ixfer_en_buf,
spc_efu_fuse_dxfer_en_buf,
.dout ({ncu_cmp_tick_enable_rep0 ,
tcu_core_running_rep0[7:0],
efu_spc_fuse_ixfer_en_buf,
efu_spc_fuse_dxfer_en_buf,
spc_msf0_dpmsff_macro__stack_10r__width_10 bank3_lat (
.scan_in(bank3_lat_scanin),
.scan_out(bank3_lat_scanout),
.se ( tcu_se_scancollar_out ),
.en ( slow_cmp_sync_en_ff),
.din ({ncu_cmp_tick_enable_rep0 ,
tcu_core_running_rep0[7:0],
ncu_wmr_vec_mask_rep0 }),
.dout ({msf0_cmp_tick_enable ,
spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5 bank4_rep1 (
.dout ({msf0_atpg_mode_buf,
tcu_mbist_user_mode_rep0,
spc_msf0_dpmsff_macro__stack_8r__width_4 bank4_lat (
.scan_in(bank4_lat_scanin),
.scan_out(bank4_lat_scanout),
.se ( tcu_se_scancollar_out ),
.en ( slow_cmp_sync_en_ff),
tcu_mbist_user_mode_rep0,
spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_4 bank5_rep1 (
.din ({tcu_shscanid [2:0],
.dout ({tcu_shscanid_rep0 [2:0],
tcu_shscan_clk_stop_rep0 })
spc_msf0_dpmsff_macro__stack_8r__width_4 bank5_lat (
.scan_in(bank5_lat_scanin),
.scan_out(bank5_lat_scanout),
.se ( tcu_se_scancollar_out ),
.en ( slow_cmp_sync_en_ff),
.din ({tcu_shscanid_rep0 [2:0],
tcu_shscan_clk_stop_rep0 }),
.dout ({msf0_shscanid [2:0],
assign bank0_lat_scanin = scan_in ;
assign bank1_lat_scanin = bank0_lat_scanout ;
assign bank2_lat_scanin = bank1_lat_scanout ;
assign bank3_lat_scanin = bank2_lat_scanout ;
assign bank4_lat_scanin = bank3_lat_scanout ;
assign bank5_lat_scanin = bank4_lat_scanout ;
assign scan_out = bank5_lat_scanout ;
// any PARAMS parms go into naming of macro
module spc_msf0_dpmsff_macro__stack_10r__width_8 (
module spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_8 (
module spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_11 (
// any PARAMS parms go into naming of macro
module spc_msf0_dpmsff_macro__stack_8r__width_8 (
module spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_1 (
// any PARAMS parms go into naming of macro
module spc_msf0_dpmsff_macro__stack_8r__width_3 (
module spc_msf0_dpbuff_macro__dbuff_16x__rep_1__stack_none__width_5 (
module spc_msf0_dpinv_macro__width_1 (
// and macro for ports = 2,3,4
module spc_msf0_dpand_macro__width_5 (
module spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_19 (
// any PARAMS parms go into naming of macro
module spc_msf0_dpmsff_macro__stack_10r__width_10 (
module spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_5 (
// any PARAMS parms go into naming of macro
module spc_msf0_dpmsff_macro__stack_8r__width_4 (
module spc_msf0_dpbuff_macro__dbuff_32x__rep_1__stack_none__width_4 (