// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: tlu_ecd_dp.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
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// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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// ========== Copyright Header End ============================================
input [67:0] data_in; // Used for generation and checking
input [7:0] ecc_in; // Used for checking only
output [7:0] syndrome; // Used for generation and checking
output cecc_err; // Used for checking only; unused for gen
output uecc_err; // Used for checking only; unused for gen
output uecc_err_; // Used for checking only; unused for gen
//////////////////////////////////////////////////////////////////////////////
// All odd positions (LSB of position set)
assign check0_bus[37:0] =
{d[67], d[65], d[63], d[61], d[59], d[57],
d[56], d[54], d[52], d[50], d[48], d[46], d[44], d[42],
d[40], d[38], d[36], d[34], d[32], d[30], d[28], d[26],
d[25], d[23], d[21], d[19], d[17], d[15], d[13], d[11],
tlu_ecd_dp_prty_macro__width_8 check0_4_pty (
.din (check0_bus [37:30] ),
tlu_ecd_dp_prty_macro__width_8 check0_3_pty (
.din (check0_bus [29:22] ),
tlu_ecd_dp_prty_macro__width_8 check0_2_pty (
.din (check0_bus [21:14] ),
tlu_ecd_dp_prty_macro__width_8 check0_1_pty (
.din (check0_bus [13:6] ),
tlu_ecd_dp_prty_macro__width_8 check0_0_pty (
tlu_ecd_dp_prty_macro__width_8 check0_pty (
// All positions with secondmost LSB set
assign check1_bus[37:0] =
{d[67:66], d[63:62], d[59:58],
d[56:55], d[52:51], d[48:47], d[44:43],
d[40:39], d[36:35], d[32:31], d[28:27],
d[25:24], d[21:20], d[17:16], d[13:12],
tlu_ecd_dp_prty_macro__width_8 check1_4_pty (
.din (check1_bus [37:30] ),
tlu_ecd_dp_prty_macro__width_8 check1_3_pty (
.din (check1_bus [29:22] ),
tlu_ecd_dp_prty_macro__width_8 check1_2_pty (
.din (check1_bus [21:14] ),
tlu_ecd_dp_prty_macro__width_8 check1_1_pty (
.din (check1_bus [13:6] ),
tlu_ecd_dp_prty_macro__width_8 check1_0_pty (
tlu_ecd_dp_prty_macro__width_8 check1_pty (
// All positions with thirdmost LSB set
assign check2_bus[35:0] =
d[56:53], d[48:45], d[40:37], d[32:29],
tlu_ecd_dp_prty_macro__width_8 check2_4_pty (
tlu_ecd_dp_prty_macro__width_8 check2_3_pty (
.din (check2_bus [28:21] ),
tlu_ecd_dp_prty_macro__width_8 check2_2_pty (
.din (check2_bus [20:13] ),
tlu_ecd_dp_prty_macro__width_8 check2_1_pty (
.din (check2_bus [12:5] ),
tlu_ecd_dp_prty_macro__width_8 check2_0_pty (
tlu_ecd_dp_prty_macro__width_8 check2_pty (
// All positions with fourthmost LSB set
assign check3_bus[35:0] =
tlu_ecd_dp_prty_macro__width_8 check3_4_pty (
tlu_ecd_dp_prty_macro__width_8 check3_3_pty (
.din (check3_bus [28:21] ),
tlu_ecd_dp_prty_macro__width_8 check3_2_pty (
.din (check3_bus [20:13] ),
tlu_ecd_dp_prty_macro__width_8 check3_1_pty (
.din (check3_bus [12:5] ),
tlu_ecd_dp_prty_macro__width_8 check3_0_pty (
tlu_ecd_dp_prty_macro__width_8 check3_pty (
// All positions with fifthmost LSB set
assign check4_bus[31:0] =
tlu_ecd_dp_prty_macro__width_32 check4_pty (
.din (check4_bus [31:0] ),
// All positions with sixthmost LSB set
assign check5_bus[31:0] =
tlu_ecd_dp_prty_macro__width_32 check5_pty (
.din (check5_bus [31:0] ),
// All positions with seventhmost LSB set
assign check6_bus[11:0] =
tlu_ecd_dp_prty_macro__width_16 check6_pty (
// Parity of the whole word (including ECC bits)
// Then xnor with e[07] to check the parity
// (or in this case, xor with e[07] to get miscompare)
assign check7_bus[74:0] =
tlu_ecd_dp_prty_macro__width_16 check7_4_pty (
tlu_ecd_dp_prty_macro__width_16 check7_3_pty (
.din (check7_bus [63:48] ),
tlu_ecd_dp_prty_macro__width_16 check7_2_pty (
.din (check7_bus [47:32] ),
tlu_ecd_dp_prty_macro__width_16 check7_1_pty (
.din (check7_bus [31:16] ),
tlu_ecd_dp_prty_macro__width_16 check7_0_pty (
.din (check7_bus [15:0] ),
tlu_ecd_dp_prty_macro__width_8 check7_inv_pty (
tlu_ecd_dp_inv_macro__width_1 e7_inv (
tlu_ecd_dp_prty_macro__width_8 check7_pty (
assign parity_incorrect =
{c7, c6, c5, c4, c3, c2, c1, c0};
// If the syndrome is zero and overall parity is correct, then no errors
// If overall parity is incorrect, then correctable
// If overall parity is correct and the syndrome is nonzero, then uncorrectable
// (| ecc_out[06:00]) & ~c7;
// Also need to factor in CERER bits
tlu_ecd_dp_nor_macro__ports_3__width_1 ecc_err_2_nor (
tlu_ecd_dp_nor_macro__ports_2__width_1 ecc_err_1_nor (
tlu_ecd_dp_nor_macro__ports_2__width_1 ecc_err_0_nor (
tlu_ecd_dp_nand_macro__ports_3__width_1 ecc_err_nand (
tlu_ecd_dp_and_macro__ports_2__width_1 cecc_err_and (
.din0 (parity_incorrect ),
tlu_ecd_dp_and_macro__ports_3__width_1 uecc_err_and (
tlu_ecd_dp_nand_macro__ports_3__width_1 uecc_err_nand (
supply0 vss; // <- port for ground
supply1 vdd; // <- port for power
// parity macro (even parity)
module tlu_ecd_dp_prty_macro__width_8 (
// parity macro (even parity)
module tlu_ecd_dp_prty_macro__width_32 (
// parity macro (even parity)
module tlu_ecd_dp_prty_macro__width_16 (
module tlu_ecd_dp_inv_macro__width_1 (
// nor macro for ports = 2,3
module tlu_ecd_dp_nor_macro__ports_3__width_1 (
// nor macro for ports = 2,3
module tlu_ecd_dp_nor_macro__ports_2__width_1 (
// nand macro for ports = 2,3,4
module tlu_ecd_dp_nand_macro__ports_3__width_1 (
// and macro for ports = 2,3,4
module tlu_ecd_dp_and_macro__ports_2__width_1 (
// and macro for ports = 2,3,4
module tlu_ecd_dp_and_macro__ports_3__width_1 (