design/sys/synopsys/script/project_sparc_cfg.scr

# ========== Copyright Header Begin ==========================================
#
# OpenSPARC T2 Processor File: project_sparc_cfg.scr
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# ========== Copyright Header End ============================================
set project_sparc_cfg   1

###########################################################################
# Specify target library specific variables
###########################################################################

source $dv_root/design/sys/synopsys/script/target_lib.scr

###########################################################################
# Include Synopsys Designware library
###########################################################################
# Designware will not be used in sparc control blocks
set synthetic_library {}
set link_path [concat  $link_library $synthetic_library]

###########################################################################
# Timing paramaters
###########################################################################

set max_transition   0.15
set max_fanout         6

# default input/output delays
set default_input_delay  0.15
set default_output_delay 0.2
set critical_range       0.30

# default number of worst path reported
set num_of_path 50

#default compile style for io is to not flatten the whole design
set compile_flatten_all 0