// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: cl_mc1.v
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// ========== Copyright Header End ============================================
module cl_mc1_adrff2b_8x ( latout, latout_l, q, q_l, so, d, l1clk, si, siclk, soclk );
wire latout, latout_l, so;
always @(l1clk or siclk or d) begin //vcs optimized code
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && !siclk) s <= m; // Load slave with master data
else if ( l1clk && siclk) begin
m <= 1'b0; // flush reset
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && siclk && !soclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if(siclk==0 && l1clk==0) m <= d;
else if(siclk && !l1clk) m <= 1'bx;
else if(siclk && l1clk) m <= si;
if(l1clk && !soclk) s<= m;
assign latout = m & l1clk;
assign latout_l = ~m & l1clk;
module cl_mc1_bistl1hdr_12x (
input l2clk; // level 2 clock, from clock grid
assign l1clk = ((((l2clk & ~clksel)|(bistclk & clksel)) & ~lce) | se) ;
module cl_mc1_bistl1hdr_16x (
input l2clk; // level 2 clock, from clock grid
assign l1clk = ((((l2clk & ~clksel)|(bistclk & clksel)) & ~lce) | se) ;
module cl_mc1_bistl1hdr_8x (
input l2clk; // level 2 clock, from clock grid
assign l1clk = ((((l2clk & ~clksel)|(bistclk & clksel)) & ~lce) | se) ;
module cl_mc1_bistlatch_10x (
assign lce = ~(pce | pce_ov);
module cl_mc1_bistlatch_20x (
assign lce = ~(pce | pce_ov);
module cl_mc1_bistlatch_4x (
assign lce = ~(pce | pce_ov);
module cl_mc1_cm_com_adff_l ( master, so, d, l1clk, si, siclk, soclk );
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !siclk && !soclk) s <= m; // Load slave with master data
else if ( l1clk && siclk && !soclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if(siclk==0 && l1clk==0) m <= d;
if(siclk && !l1clk) m <= 1'bx;
else if(siclk && l1clk) m <= si;
module cl_mc1_cm_com_adff_r ( master, so, d, l1clk, si, siclk, soclk );
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !siclk && !soclk) s <= m; // Load slave with master data
else if ( l1clk && siclk && !soclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if(siclk==0 && l1clk==0) m <= d;
if(siclk && !l1clk) m <= 1'bx;
else if(siclk && l1clk) m <= si;
module cl_mc1_cm_com_dff ( master, master_l, so, d, l1clk, si, siclk, soclk );
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !siclk && !soclk) s <= m; // Load slave with master data
else if ( l1clk && siclk && !soclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if(siclk==0 && l1clk==0) m <= d;
if(siclk && !l1clk) m <= 1'bx;
else if(siclk && l1clk) m <= si;
module cl_mc1_cm_nor_msff ( q, so, din, clear, l1clk, si, siclk, soclk );
// Level sensitive in SCAN_MODE
// Edge triggered when not in SCAN_MODE
wire l1clk, siclk, soclk;
always @(l1clk or siclk or soclk or din or clear or si)
if (!l1clk && !siclk) m <= ~(din | clear); // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
else if ( l1clk && !siclk && !soclk) q <= m; // Load slave with master data
if ( l1clk && siclk && !soclk) q <= si; // Flush
if (!siclk && !soclk) q <= ~(din | clear);
// created June 6, 2005, ln
module cl_mc1_gate_antenna_50k ( in );
// created June 6, 2005, ln
module cl_mc1_gate_antenna_5k ( in );
module cl_mc1_irf_lat_rsto (
if (l1clk == 1'b0) m <= d;
module cl_mc1_irf_lat_swl (
if (l1clk == 1'b0) m <= d;
module cl_mc1_irf_msff_4x ( q, so, d, l1clk, si, siclk, soclk );
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && siclk && !soclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if(siclk==0 && l1clk==0) m <= d;
if(siclk && !l1clk) m <= 1'bx;
else if(siclk && l1clk) m <= si;
module cl_mc1_l1driver_12x (
input l2clk; // level 2 clock, from clock grid
input l1en; // Clock enable for local power savings
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1driver_16x (
input l2clk; // level 2 clock, from clock grid
input l1en; // Clock enable for local power savings
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1driver_24x (
input l2clk; // level 2 clock, from clock grid
input l1en; // Clock enable for local power savings
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1driver_32x (
input l2clk; // level 2 clock, from clock grid
input l1en; // Clock enable for local power savings
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1driver_48x (
input l2clk; // level 2 clock, from clock grid
input l1en; // Clock enable for local power savings
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1driver_4x (
input l2clk; // level 2 clock, from clock grid
input l1en; // Clock enable for local power savings
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1driver_64x (
input l2clk; // level 2 clock, from clock grid
input l1en; // Clock enable for local power savings
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1driver_8x (
input l2clk; // level 2 clock, from clock grid
input l1en; // Clock enable for local power savings
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1driver_by2_24x (
input l2clk; // level 2 clock, from clock grid
input l1en; // Clock enable for local power savings
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1driver_by2_32x (
input l2clk; // level 2 clock, from clock grid
input l1en; // Clock enable for local power savings
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1driver_by2_48x (
input l2clk; // level 2 clock, from clock grid
input l1en; // Clock enable for local power savings
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1driver_by2_64x (
input l2clk; // level 2 clock, from clock grid
input l1en; // Clock enable for local power savings
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
// Edge modeled Enable latch
module cl_mc1_l1enable_12x (
always @ (negedge l2clk )
// logically correct model
// always @ (l2clk or pce or pce_ov)
// if (l2clk == 1'b0) l1en <= (pce | pce_ov);
// Edge modeled Enable latch
module cl_mc1_l1enable_16x (
always @ (negedge l2clk )
// logically correct model
// always @ (l2clk or pce or pce_ov)
// if (l2clk == 1'b0) l1en <= (pce | pce_ov);
// Edge modeled Enable latch
module cl_mc1_l1enable_24x (
always @ (negedge l2clk )
// logically correct model
// always @ (l2clk or pce or pce_ov)
// if (l2clk == 1'b0) l1en <= (pce | pce_ov);
// Edge modeled Enable latch
module cl_mc1_l1enable_32x (
always @ (negedge l2clk )
// logically correct model
// always @ (l2clk or pce or pce_ov)
// if (l2clk == 1'b0) l1en <= (pce | pce_ov);
// Edge modeled Enable latch
module cl_mc1_l1enable_48x (
always @ (negedge l2clk )
// logically correct model
// always @ (l2clk or pce or pce_ov)
// if (l2clk == 1'b0) l1en <= (pce | pce_ov);
// Edge modeled Enable latch
module cl_mc1_l1enable_4x (
always @ (negedge l2clk )
// logically correct model
// always @ (l2clk or pce or pce_ov)
// if (l2clk == 1'b0) l1en <= (pce | pce_ov);
// Edge modeled Enable latch
module cl_mc1_l1enable_64x (
always @ (negedge l2clk )
// logically correct model
// always @ (l2clk or pce or pce_ov)
// if (l2clk == 1'b0) l1en <= (pce | pce_ov);
// Edge modeled Enable latch
module cl_mc1_l1enable_8x (
always @ (negedge l2clk )
// logically correct model
// always @ (l2clk or pce or pce_ov)
// if (l2clk == 1'b0) l1en <= (pce | pce_ov);
module cl_mc1_l1hdr_16x (
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1hdr_24x (
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1hdr_32x (
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1hdr_48x (
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1hdr_64x (
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_l1hdr_by4_64x (
input l2clk; // level 2 clock, from clock grid
input pce; // Clock enable for local power savings
input pce_ov; // TCU sourced clock enable override for testing
input stop; // TCU/CCU sourced clock stop for debug
always @ (l2clk or stop or pce or pce_ov)
if (~l2clk) l1en <= (~stop & (pce | pce_ov));
always @ (negedge l2clk )
l1en <= (~stop & ( pce | pce_ov ));
assign l1clk = (l2clk & l1en) | se; // se is async and highest priority
module cl_mc1_rep_m6_32x (
module cl_mc1_rrf_msff_8x ( q, so, d, l1clk, si, siclk, soclk );
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && siclk && !soclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if(siclk==0 && l1clk==0) m <= d;
if(siclk && !l1clk) m <= 1'bx;
else if(siclk && l1clk) m <= si;
module cl_mc1_rrf_msff_mo_8x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
wire mq, mq_l, q, q_l, so;
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; //Load master with data
else if ( l1clk && siclk) m <= si; //Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan
if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && !soclk && siclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if (!siclk && !l1clk) m <= d;
else if ( siclk && !l1clk) m <= 1'bx;
else if ( siclk && l1clk) m <= si;
if ( l1clk && !soclk) s <= m;
assign mq = m & (and_clk & l1clk);
assign mq_l = ~m & (and_clk & l1clk);
wire and_clk_unused = and_clk;
module cl_mc1_scm_msff_flop_4x ( q, q_l, so, d, l1clk, si, siclk, soclk);
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && siclk && !soclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if(siclk==0 && l1clk==0) m = d;
else if(siclk && !l1clk) m = 1'bx;
if(siclk && l1clk) m = si;
if(l1clk && !soclk) s = m;
module cl_mc1_scm_msff_lat_4x ( latout, q, q_l, so, d, l1clk, si, siclk, soclk);
always @(l1clk or siclk or d) begin //vcs optimized code
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && !siclk) s <= m; // Load slave with master data
else if ( l1clk && siclk) begin
m <= 1'b0; // flush reset
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && siclk && !soclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if(siclk==0 && l1clk==0) m = d;
else if(siclk && !l1clk) m = 1'bx;
if(siclk && l1clk) m = si;
if(l1clk && !soclk) s = m;
module cl_mc1_sram_msff_mo_16x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
wire mq, mq_l, q, q_l, so;
always @(l1clk or siclk or d) begin //vcs optimized code
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && !siclk) s <= m; // Load slave with master data
else if ( l1clk && siclk) begin
m <= 1'b0; // flush reset
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; //Load master with data
else if ( l1clk && siclk) m <= si; //Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan
if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && !soclk && siclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if (!siclk && !l1clk) m <= d;
else if ( siclk && !l1clk) m <= 1'bx;
else if ( siclk && l1clk) m <= si;
if ( l1clk && !soclk) s <= m;
assign mq = m & (and_clk & l1clk);
assign mq_l = ~m & (and_clk & l1clk);
wire and_clk_unused = and_clk;
module cl_mc1_sram_msff_mo_32x ( mq, mq_l, q, so, d, l1clk, si, siclk, soclk, and_clk );
always @(l1clk or siclk or d) begin //vcs optimized code
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && !siclk) s <= m; // Load slave with master data
else if ( l1clk && siclk) begin
m <= 1'b0; // flush reset
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; //Load master with data
else if ( l1clk && siclk) m <= si; //Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan
if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && !soclk && siclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if (!siclk && !l1clk) m <= d;
else if ( siclk && !l1clk) m <= 1'bx;
else if ( siclk && l1clk) m <= si;
if ( l1clk && !soclk) s <= m;
assign mq = m & (and_clk & l1clk);
assign mq_l = ~m & (and_clk & l1clk);
wire and_clk_unused = and_clk;
module cl_mc1_sram_msff_mo_4x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
wire mq, mq_l, q, q_l, so;
always @(l1clk or siclk or d) begin //vcs optimized code
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && !siclk) s <= m; // Load slave with master data
else if ( l1clk && siclk) begin
m <= 1'b0; // flush reset
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; //Load master with data
else if ( l1clk && siclk) m <= si; //Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan
if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && !soclk && siclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if (!siclk && !l1clk) m <= d;
else if ( siclk && !l1clk) m <= 1'bx;
else if ( siclk && l1clk) m <= si;
if ( l1clk && !soclk) s <= m;
assign mq = m & (and_clk & l1clk);
assign mq_l = ~m & (and_clk & l1clk);
wire and_clk_unused = and_clk;
module cl_mc1_sram_msff_mo_8x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
wire mq, mq_l, q, q_l, so;
always @(l1clk or siclk or d) begin //vcs optimized code
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && !siclk) s <= m; // Load slave with master data
else if ( l1clk && siclk) begin
m <= 1'b0; // flush reset
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; //Load master with data
else if ( l1clk && siclk) m <= si; //Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan
if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && !soclk && siclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if (!siclk && !l1clk) m <= d;
else if ( siclk && !l1clk) m <= 1'bx;
else if ( siclk && l1clk) m <= si;
if ( l1clk && !soclk) s <= m;
assign mq = m & (and_clk & l1clk);
assign mq_l = ~m & (and_clk & l1clk);
wire and_clk_unused = and_clk;
module cl_mc1_sram_msff_mo_nand2_16x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk );
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !siclk && !soclk) s <= m; // Load slave with master data
else if ( l1clk && siclk && !soclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if (!siclk && !l1clk) m <= d;
else if ( siclk && !l1clk) m <= 1'bx;
else if ( siclk && l1clk) m <= si;
if ( l1clk && !soclk) s <= m;
assign mq_l = ~m & l1clk;
module cl_mc1_sram_msff_mo_nand2_8x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk );
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !siclk && !soclk) s <= m; // Load slave with master data
else if ( l1clk && siclk && !soclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if (!siclk && !l1clk) m <= d;
else if ( siclk && !l1clk) m <= 1'bx;
else if ( siclk && l1clk) m <= si;
if ( l1clk && !soclk) s <= m;
assign mq_l = ~m & l1clk;
module cl_mc1_sram_msff_mo_nand3_16x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
wire mq, mq_l, q, q_l, so;
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; //Load master with data
else if ( l1clk && siclk) m <= si; //Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan
if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && !soclk && siclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if (!siclk && !l1clk) m <= d;
else if ( siclk && !l1clk) m <= 1'bx;
else if ( siclk && l1clk) m <= si;
if ( l1clk && !soclk) s <= m;
assign mq = m & (and_clk & l1clk);
assign mq_l = ~m & (and_clk & l1clk);
wire and_clk_unused = and_clk;
module cl_mc1_sram_msff_mo_nand3_8x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
wire mq, mq_l, q, q_l, so;
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; //Load master with data
else if ( l1clk && siclk) m <= si; //Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan
if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && !soclk && siclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if (!siclk && !l1clk) m <= d;
else if ( siclk && !l1clk) m <= 1'bx;
else if ( siclk && l1clk) m <= si;
if ( l1clk && !soclk) s <= m;
assign mq = m & (and_clk & l1clk);
assign mq_l = ~m & (and_clk & l1clk);
wire and_clk_unused = and_clk;
module cl_mc1_sram_msff_mo_opt_16x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
wire mq, mq_l, q, q_l, so;
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; //Load master with data
else if ( l1clk && siclk) m <= si; //Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan
if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && !soclk && siclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if (!siclk && !l1clk) m <= d;
else if ( siclk && !l1clk) m <= 1'bx;
else if ( siclk && l1clk) m <= si;
if ( l1clk && !soclk) s <= m;
assign mq = m & (and_clk & l1clk);
assign mq_l = ~m & (and_clk & l1clk);
wire and_clk_unused = and_clk;
module cl_mc1_sram_msff_mo_opt_8x ( mq, mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
wire mq, mq_l, q, q_l, so;
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; //Load master with data
else if ( l1clk && siclk) m <= si; //Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; //Conflict between data and scan
if (l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && !soclk && siclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if (!siclk && !l1clk) m <= d;
else if ( siclk && !l1clk) m <= 1'bx;
else if ( siclk && l1clk) m <= si;
if ( l1clk && !soclk) s <= m;
assign mq = m & (and_clk & l1clk);
assign mq_l = ~m & (and_clk & l1clk);
wire and_clk_unused = and_clk;
module cl_mc1_sram_msff_mo_phaseb_8x ( phaseb_mq, phaseb_mq_l, q, q_l, so, d, l1clk, si, siclk, soclk, and_clk );
always @(l1clk or siclk or soclk or d or si)
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !siclk && !soclk) q <= m; // Load slave with master data
else if ( l1clk && siclk && !soclk) q <= si; // Flush
always @(l1clk or d or si or siclk) begin
if (!siclk && !l1clk) m <= d;
else if ( siclk && !l1clk) m <= 1'bx;
else if ( siclk && l1clk) m <= si;
if ( l1clk && !soclk) q <= m;
assign phaseb_mq = ~and_clk && q;
assign phaseb_mq_l = ~and_clk && q_l;
wire and_clk_unused = and_clk;
module cl_mc1_tcam_msff_4x ( q, so, d, l1clk, si, siclk, soclk );
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && siclk && !soclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if(siclk==0 && l1clk==0) m <= d;
if(siclk && !l1clk) m <= 1'bx;
else if(siclk && l1clk) m <= si;
module cl_mc1_tisram_bla_4x (q_a, d_b, l1clk);
always @(l1clk or d_b) begin
module cl_mc1_tisram_blb_4x (q_b, d_a, l1clk);
always @(l1clk or d_a) begin
module cl_mc1_tisram_blbi_8x (q_b_l, d_a, l1clk);
always @(l1clk or d_a) begin
if(l1clk==0) q_b_l <= ~d_a;
module cl_mc1_tisram_msff_16x ( latout, latout_l, so, d, l1clk, si,
wire latout, latout_l, so;
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && siclk && !soclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if(siclk==0 && l1clk==0) m <= d;
if(siclk && !l1clk) m <= 1'bx;
else if(siclk && l1clk) m <= si;
module cl_mc1_tisram_msff_8x ( latout, latout_l, so, d, l1clk, si,
wire latout, latout_l, so;
always @(l1clk or siclk or soclk or d or si) begin
if (!l1clk && !siclk) m <= d; // Load master with data
else if ( l1clk && siclk) m <= si; // Load master with scan or flush
else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan
if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data
else if (l1clk && siclk && !soclk) s <= si; // Flush
always @(l1clk or d or si or siclk) begin
if(siclk==0 && l1clk==0) m <= d;
if(siclk && !l1clk) m <= 1'bx;
else if(siclk && l1clk) m <= si;