// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: n2_dta_sp_1920b_cust.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
module n2_dta_sp_1920b_cust (
wire dff_inputs1_scanout;
wire [8:0] dff_inputs1_unused;
wire dff_inputs2_scanout;
wire [0:0] index_y_unused;
wire dff_inputs3_scanout;
wire [1:0] dff_inputs3_unused;
wire dff_inputs4_scanout;
input [6:0] index0_x; // address0 (used for read)
input [6:0] index1_x; // address1 (used for write)
input index_sel_x; // selects between index1 and index0
input [1:0] wrway_x; // way to write to
input rdreq_x; // read enable
input wrreq_x; // write enable
// 0in bits_on -var {rdreq_x,wrreq_x} -max 1 -message "Attempt to read AND write dtag on same cycle"
// 0in custom -fire ((rdreq_x | wrreq_x) & ~dta_clken) -message "Attempt to read or write with clock disabled"
input [29:0] wrtag_x; // write data
input dta_clken; // array clock enable
output [29:0] rdtag_w0_y; // read data split into 4 ports
output [29:0] rdtag_w1_y; // read data
output [29:0] rdtag_w2_y; // read data
output [29:0] rdtag_w3_y; // read data
input tcu_se_scancollar_in;
input tcu_array_wr_inhibit;
// synopsys translate_off
wire pce_ov = tcu_pce_ov;
//================================================
//================================================
// This clock gates the wrtag input flops.
n2_dta_sp_1920b_cust_l1clkhdr_ctl_macro l1ch_din (
.se (tcu_se_scancollar_in),
// This clock gates the other input flops and latches.
// It will be not be power managed.
n2_dta_sp_1920b_cust_l1clkhdr_ctl_macro l1ch_in (
.se (tcu_se_scancollar_in),
// This clock gates the array and internal logic.
n2_dta_sp_1920b_cust_l1clkhdr_ctl_macro l1ch_array (
//=========================================================================================
//=========================================================================================
// 2:1 mux on address input
// address inputs are critical and this mux needs to be merged with the receiving flop.
assign index_x[6:0] = index_sel_x ? index1_x[6:0] : index0_x[6:0];
n2_dta_sp_1920b_cust_tisram_msff_macro__width_9 dff_inputs1 (
.scan_in(dff_inputs1_scanin),
.scan_out(dff_inputs1_scanout),
.latout_l(dff_inputs1_unused[8:0]),
n2_dta_sp_1920b_cust_msff_ctl_macro__width_1 dff_inputs2 (
.scan_in(dff_inputs2_scanin),
.scan_out(dff_inputs2_scanout),
.dout (index_y_unused[0]),
n2_dta_sp_1920b_cust_tisram_msff_macro__width_2 dff_inputs3 (
.scan_in(dff_inputs3_scanin),
.scan_out(dff_inputs3_scanout),
.latout ({rdreq_b,wrreq_b}),
.latout_l(dff_inputs3_unused[1:0]),
n2_dta_sp_1920b_cust_msff_ctl_macro__width_2 dff_inputs4 (
.scan_in(dff_inputs4_scanin),
.scan_out(dff_inputs4_scanout),
.din ({rdreq_x,wrreq_x}),
.dout ({rdreq_a,wrreq_a}),
n2_dta_sp_1920b_cust_msff_ctl_macro__width_30 dff_wrtag (
.scan_in(dff_wrtag_scanin),
.scan_out(dff_wrtag_scanout),
n2_dta_sp_1920b_cust_inv_macro__width_3 way_inv (
.din ({wrway_y[1:0], tcu_array_wr_inhibit}),
.dout ({wrway_y_[1:0],wr_inhibit_})
assign wr_inhibit = tcu_array_wr_inhibit;
n2_dta_sp_1920b_cust_and_macro__ports_4__width_4 way_and (
.din0 ({wrreq_b, wrreq_b, wrreq_b, wrreq_b}),
.din1 ({wrway_y [0],wrway_y_[0],wrway_y [0],wrway_y_[0]}),
.din2 ({wrway_y [1],wrway_y [1],wrway_y_[1],wrway_y_[1]}),
.din3 ({4{wr_inhibit_}}),
n2_dta_sp_1920b_array way0 (
.dout (rdtag_w0_y[29:0]),
n2_dta_sp_1920b_array way1 (
.dout (rdtag_w1_y[29:0]),
n2_dta_sp_1920b_array way2 (
.dout (rdtag_w2_y[29:0]),
n2_dta_sp_1920b_array way3 (
.dout (rdtag_w3_y[29:0]),
assign dff_inputs1_scanin = scan_in ;
assign dff_inputs2_scanin = dff_inputs1_scanout ;
assign dff_inputs3_scanin = dff_inputs2_scanout ;
assign dff_inputs4_scanin = dff_inputs3_scanout ;
assign dff_wrtag_scanin = dff_inputs4_scanout ;
assign scan_out = dff_wrtag_scanout ;
// any PARAMS parms go into naming of macro
module n2_dta_sp_1920b_cust_l1clkhdr_ctl_macro (
// macro for cl_mc1_tisram_msff_{16,8}x flops
module n2_dta_sp_1920b_cust_tisram_msff_macro__width_9 (
//place::generic_place($width,$stack,$left);
// any PARAMS parms go into naming of macro
module n2_dta_sp_1920b_cust_msff_ctl_macro__width_1 (
assign fdin[0:0] = din[0:0];
// macro for cl_mc1_tisram_msff_{16,8}x flops
module n2_dta_sp_1920b_cust_tisram_msff_macro__width_2 (
//place::generic_place($width,$stack,$left);
// any PARAMS parms go into naming of macro
module n2_dta_sp_1920b_cust_msff_ctl_macro__width_2 (
assign fdin[1:0] = din[1:0];
// any PARAMS parms go into naming of macro
module n2_dta_sp_1920b_cust_msff_ctl_macro__width_30 (
assign fdin[29:0] = din[29:0];
.so({so[28:0],scan_out}),
module n2_dta_sp_1920b_cust_inv_macro__width_3 (
// and macro for ports = 2,3,4
module n2_dta_sp_1920b_cust_and_macro__ports_4__width_4 (
module n2_dta_sp_1920b_array (
input rd_en_b; // comes on negedge
input wr_en_b; // comes on negedge (way specific)
input rd_en_a; // comes on posedge
input wr_en_a; // comes on posedge (not way specific)
input [`ADDRBITS-1:0] addr; // comes on negedge
input wr_inhibit; // async
input [`WIDTH-1:0] din; // comes on posedge
output [`WIDTH-1:0] dout;
reg [`WIDTH-1:0] mem[`ENTRIES-1:0];
reg [`WIDTH-1:0] local_dout;
assign rd_en_b_unused = rd_en_b;
for (i=0; i<`ENTRIES; i=i+1) begin
local_dout = {`WIDTH{1'b0}};
always @(negedge clk) begin
always @(posedge clk) begin
local_dout[`WIDTH-1:0] <= mem[addr];
assign dout[`WIDTH-1:0] = local_dout[`WIDTH-1:0] & {`WIDTH{rd_en_a & ~wr_en_a & ~wr_inhibit}};