tools/fpga/fpga_synth_synplicity_default.prj

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# OpenSPARC T2 Processor File: fpga_synth_synplicity_default.prj
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########default synplicity project file/template############
####top defined by fpga_synth
####flist defined by fpga_synth
# Add Constraints file

add_file -constraint $DV_ROOT/tools/fpga/fpga_synth_synplicity_mapper.sdc

####
###set_option -top_module "t2"


#simulation options
set_option -write_verilog 1


#gate output dir
impl -add t2_synth -type fpga


#compilation/mapping options
set_option -default_enum_encoding default
set_option -resource_sharing 1
set_option -use_fsm_explorer 0

#map options
set_option -frequency 16.000
set_option -run_prop_extract 1
set_option -fanout_limit 10000
set_option -disable_io_insertion 0
set_option -pipe 1
set_option -update_models_cp 0
set_option -enable_prepacking 1
set_option -retiming 0
set_option -no_sequential_opt 0
set_option -fixgatedclocks 3
set_option -fixgeneratedclocks 3
set_option -effort default


#sequential_optimizations options
set_option -symbolic_fsm_compiler 1

#planner options
set_option -write_pp_verilog 1
set_option -write_pp_vhdl 1
set_option -write_pp_mixed 1
set_option -write_pp_srs 1

#simulation options
set_option -write_verilog 1
set_option -write_vhdl 0

#VIF options
set_option -write_vif 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

############################
#implementation attributes
#
set_option -vlog_std v2001
set_option -dup 0
set_option -auto_constrain_io 1
set_option -project_relative_includes 1
set_option -enable64bit 1
set_option -suppress_remap 1