Initial commit of OpenSPARC T2 design and verification files.

[OpenSPARC-T2-DV] / tools / src / nas,5.n2.os.2 / home / common / common.conf

//
// pli-socket options
//
//#if defined(RTL) || defined(PLI_REPLAY)
OBJECT socket0 TYPE pli-socket {
#if defined(FORCE_PC)
       force_pc: 1
#else
       force_pc: 0
#endif
#if !defined(NOINT_SYNC) && (defined(RTL) || defined(PLI_REPLAY))
       // int_sync is enabled
       int_model: 1
#else
       int_model: 0    
#endif
#if !defined(NOLDST_SYNC) && (defined(RTL) || defined(PLI_REPLAY))
       // msync is enabled
       mem_model: 1
#else
       mem_model: 0    
#endif
#ifdef VERA_SOCKET
       cmd_intf: 0
#else
       cmd_intf: 1
#endif
#ifdef PLI_REPLAY
       replay_log: PLI_REPLAY
       socket: 0
       open: 0
#elif defined(CSOCKET)
       replay_log: 0
       socket: CSOCKET
       open: 1 
#else
       replay_log: 0
       socket: 0
       open: 0
#endif
       close: 0
       test: 0
#ifdef PLI_LOG
       pli_log: PLI_LOG
#else
       pli_log: 0
#endif
#if defined(NO_REG_CMP)
       reg_cmp: 0
#elif defined(REG_CMP)
       reg_cmp: REG_CMP
#else
       reg_cmp: 1
#endif
#if defined(PLI_RTL_DEBUG)
       debug_level: 9
#elif defined(PLI_DEBUG)
       debug_level: PLI_DEBUG
#else
       // default shows trap & instructions
       debug_level: 2
#endif
#if !defined(NOTLB_SYNC)
       tlb_sync: 1
#else
       tlb_sync: 0
#endif
#if defined(TLB_SYNC_DEBUG)
       tlb_debug: TLB_SYNC_DEBUG
#else
       tlb_debug: 0
#endif
#if defined(CMP_REG_CMP)
       cmp_cmp: CMP_REG_CMP
#endif
#if defined(MMU_REG_CMP)
       mmu_cmp: MMU_REG_CMP
#endif
#if defined(SHOW_TRAP)
       show_trap: SHOW_TRAP
#else
       show_trap: 0
#endif
#if defined(ENABLE_RAS)
       enable_ras: ENABLE_RAS
#else
       enable_ras: 0
#endif
}

//#endif // defined(RTL) || defined(PLI_REPLAY)

//
// swvmem0: msync, tsoChecker, and pmask related options
//
#if defined(MOM)

OBJECT mom0 TYPE mom {
       queue: th00
       enable_sim: 1
       wait-mode: 0
#if defined(MOM_DEBUG)
       DEBUG: 1
#endif
#if defined(MOM_SO_PATH)
       so_path: MOM_SO_PATH
#endif
}

#else   // if defined(MOM)

OBJECT swvmem0 TYPE swerver-memory {
#if defined(RTL) || defined(PLI_REPLAY)
       irq:   irq0
#endif
#if defined(MEM_DISABLE) && !defined(PLI_REPLAY)
       snoop: 0
#else
       snoop: 1
#endif
#if defined(TSO_CHECKER) && !defined(NO_TSO_CHECKER)
       tso_checker: 1
#else
       tso_checker: 0
#endif
#if defined(DIS_DEBUG)
       debug_level: 0
#elif defined(TSO_DEBUG)
       debug_level: 2
#elif defined(MEM_DEBUG)
       debug_level: MEM_DEBUG
#else
       debug_level: 0
#endif
#if defined(MEM_IFETCH) && !defined(NO_MEM_IFETCH)
       ifetch: 1
#else
       ifetch: 0
#endif
       queue: th00
// CMP masking
#define XSTR(M) STR(M)
#define STR(M)  #M
#if defined(THREAD_MASK0)
       thread_mask0: XSTR(THREAD_MASK0)
#else
       thread_mask0: "01"
#endif
#if defined(THREAD_MASK1)
       thread_mask1: XSTR(THREAD_MASK1)
#endif
#if defined(THREAD_MASK2)
       thread_mask2: XSTR(THREAD_MASK2)
#endif
#if defined(THREAD_MASK3)
       thread_mask3: XSTR(THREAD_MASK3)
#endif
}

#endif   // if defined(MOM)

//=================== the following OBJECTs are not used ====================//

OBJECT sim TYPE sim {
       cpu_switch_time: 1
       time_model: "on"
       continue_disabled: 0
#if !defined(NOLDST_SYNC)
       instruction_profile_mode: instruction-cache-access-trace
       instruction_profile_line_size: 4
#endif
}

#ifdef CIOP0
############################################# chip 0 IO devices
OBJECT irq0 TYPE swerver-interrupt {
       thread_base: 0
       queue: th00
}

OBJECT ciop0 TYPE swerver-io-device {
       physical_memory: phys_mem0
       irq:             irq0
       queue:           th00
}
OBJECT bsc0 TYPE bsc-device {
       queue:           th00
}
OBJECT egress0 TYPE egress-device {
       queue:           th00
}
OBJECT ingress0 TYPE ingress-device {
       queue:           th00
}
OBJECT rdma0 TYPE rdma-device {
       queue:           th00
}
OBJECT echo0 TYPE echo-device {
       queue:           th00
}
#else
OBJECT memory_ciop TYPE ram {
       image: memory_ciop_image
}
OBJECT memory_ciop_image TYPE image {
       size: 0x7f00000000
       queue: th00
}
#endif

#undef sparc

OBJECT irqbus0 TYPE sparc-irq-bus {
}

#if defined(RTL) || defined(PLI_REPLAY)
OBJECT irq0 TYPE swerver-interrupt {
       thread_base: 0
       need_ssi: 1
       queue: th00
}
#endif

#ifdef SP0
OBJECT swvp0 TYPE swerver-processor {
       thread0: th00
       thread1: th01
       thread2: th02
       thread3: th03
       thread4: th04
       thread5: th05
       thread6: th06
       thread7: th07
       mmu:swmmu0
}
OBJECT swmmu0 TYPE swerver-proc-mmu {
}

OBJECT th00 TYPE niagara2 {
       freq_mhz: 800
       mmu: stmmu00
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 0))
       irq_bus: irqbus0
       thread_id: 0
       other_threads: (th01, th02, th03, th04, th05, th06, th07)
       queue: th00
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu00 TYPE swerver-thread-mmu {
       thread-status: 1
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       intr_trap_type: 0x60
       stream_cmpl_trap_type: 0x70
       ma_cmpl_trap_type: 0x74
       model-real-sfar: 1
#if defined(N1_ASI)
       n2-legacy-asi: 1
#endif
#if defined(RTL) || defined(PLI_REPLAY)
       ignore_asi_0x73: 1
       match_rtl: 1
#endif
#if defined(MOM)
       mom_intf: 1
#endif
}

OBJECT spu00 TYPE swerver-spu {
       queue: th00
       thread: th00
}

OBJECT th01 TYPE niagara2 {
       freq_mhz: 800
       mmu: stmmu01
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 1))
       irq_bus: irqbus0
       queue: th01
       thread_id: 1
       other_threads: (
                       th00,
                       th02,
                       th03,
                       th04,
                       th05,
                       th06,
                       th07
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu01 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu01 TYPE swerver-spu {
       queue: th01
       thread: th01
}

OBJECT th02 TYPE niagara2 {
       freq_mhz: 800
       mmu: stmmu02
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 2))
       irq_bus: irqbus0
       queue: th02
       thread_id: 2
       other_threads: (
                       th00,
                       th01,
                       th03,
                       th04,
                       th05,
                       th06,
                       th07
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu02 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu02 TYPE swerver-spu {
       queue: th02
       thread: th02
}

OBJECT th03 TYPE niagara2 {
       freq_mhz: 800
       mmu: stmmu03
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 3))
       irq_bus: irqbus0
       queue: th03
       thread_id: 3
       other_threads: (
                       th00,
                       th01,
                       th02,
                       th04,
                       th05,
                       th06,
                       th07
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu03 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu03 TYPE swerver-spu {
       queue: th03
       thread: th03
}

OBJECT th04 TYPE niagara2 {
       freq_mhz: 800
       mmu: stmmu04
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 4))
       irq_bus: irqbus0
       queue: th04
       thread_id: 4
       other_threads: (
                       th00,
                       th01,
                       th02,
                       th03,
                       th05,
                       th06,
                       th07
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu04 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu04 TYPE swerver-spu {
       queue: th04
       thread: th04
}

OBJECT th05 TYPE niagara2 {
       freq_mhz: 800
       mmu: stmmu05
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 5))
       irq_bus: irqbus0
       queue: th05
       thread_id: 5
       other_threads: (
                       th00,
                       th01,
                       th02,
                       th03,
                       th04,
                       th06,
                       th07
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu05 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu05 TYPE swerver-spu {
       queue: th05
       thread: th05
}

OBJECT th06 TYPE niagara2 {
       freq_mhz: 800
       mmu: stmmu06
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 6))
       irq_bus: irqbus0
       queue: th06
       thread_id: 6
       other_threads: (
                       th00,
                       th01,
                       th02,
                       th03,
                       th04,
                       th05,
                       th07
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu06 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu06 TYPE swerver-spu {
       queue: th06
       thread: th06
}

OBJECT th07 TYPE niagara2 {
       freq_mhz: 800
       mmu: stmmu07
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 7))
       irq_bus: irqbus0
       queue: th07
       thread_id: 7
       other_threads: (
                       th00,
                       th01,
                       th02,
                       th03,
                       th04,
                       th05,
                       th06
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu07 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu07 TYPE swerver-spu {
       queue: th07
       thread: th07
}

#endif  // SP0


#ifdef SP1

OBJECT swvp1 TYPE swerver-processor {
       thread0: th08
       thread1: th09
       thread2: th10
       thread3: th11
       thread4: th12
       thread5: th13
       thread6: th14
       thread7: th15
       mmu:swmmu1
}

OBJECT swmmu1 TYPE swerver-proc-mmu {
}

OBJECT th08 TYPE niagara2 {
       mmu: stmmu08
       queue: th08
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 8))
       irq_bus: irqbus0
       thread_id: 0
       other_threads: (
                       th09,
                       th10,
                       th11,
                       th12,
                       th13,
                       th14,
                       th15
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu08 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu08 TYPE swerver-spu {
       queue: th08
       thread: th08
}
OBJECT th09 TYPE niagara2 {
       mmu: stmmu09
       queue: th09
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 9))
       irq_bus: irqbus0
       thread_id: 1
       other_threads: (
                       th08,
                       th10,
                       th11,
                       th12,
                       th13,
                       th14,
                       th15
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu09 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu09 TYPE swerver-spu {
       queue: th09
       thread: th09
}
OBJECT th10 TYPE niagara2 {
       mmu: stmmu10
       queue: th10
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 10))
       irq_bus: irqbus0
       thread_id: 2
       other_threads: (
                       th08,
                       th09,
                       th11,
                       th12,
                       th13,
                       th14,
                       th15
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu10 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu10 TYPE swerver-spu {
       queue: th10
       thread: th10
}

OBJECT th11 TYPE niagara2 {
       mmu: stmmu11
       queue: th11
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 11))
       irq_bus: irqbus0
       thread_id: 3
       other_threads: (
                       th08,
                       th09,
                       th10,
                       th12,
                       th13,
                       th14,
                       th15
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu11 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu11 TYPE swerver-spu {
       queue: th11
       thread: th11
}

OBJECT th12 TYPE niagara2 {
       mmu: stmmu12
       queue: th12
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 12))
       irq_bus: irqbus0
       thread_id: 4
       other_threads: (
                       th08,
                       th09,
                       th10,
                       th11,
                       th13,
                       th14,
                       th15
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu12 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu12 TYPE swerver-spu {
       queue: th12
       thread: th12
}

OBJECT th13 TYPE niagara2 {
       mmu: stmmu13
       queue: th13
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 13))
       irq_bus: irqbus0
       thread_id: 5
       other_threads: (
                       th08,
                       th09,
                       th10,
                       th11,
                       th12,
                       th14,
                       th15
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu13 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu13 TYPE swerver-spu {
       queue: th13
       thread: th13
}

OBJECT th14 TYPE niagara2 {
       mmu: stmmu14
       queue: th14
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 14))
       irq_bus: irqbus0
       thread_id: 6
       other_threads: (
                       th08,
                       th09,
                       th10,
                       th11,
                       th12,
                       th13,
                       th15
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu14 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu14 TYPE swerver-spu {
       queue: th14
       thread: th14
}

OBJECT th15 TYPE niagara2 {
       mmu: stmmu15
       queue: th15
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 15))
       irq_bus: irqbus0
       thread_id: 7
       other_threads: (
                       th08,
                       th09,
                       th10,
                       th11,
                       th12,
                       th13,
                       th14
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu15 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu15 TYPE swerver-spu {
       queue: th15
       thread: th15
}


#endif

#ifdef SP2

OBJECT swvp2 TYPE swerver-processor {
       thread0: th16
       thread1: th17
       thread2: th18
       thread3: th19
       thread4: th20
       thread5: th21
       thread6: th22
       thread7: th23
       mmu:swmmu2
}

OBJECT swmmu2 TYPE swerver-proc-mmu {
}

OBJECT th16 TYPE niagara2 {
       mmu: stmmu16
       queue: th16
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 16))
       irq_bus: irqbus0
       thread_id: 0
       other_threads: (
                       th17,
                       th18,
                       th19,
                       th20,
                       th21,
                       th22,
                       th23
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu16 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu16 TYPE swerver-spu {
       queue: th16
       thread: th16
}

OBJECT th17 TYPE niagara2 {
       mmu: stmmu17
       queue: th17
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 17))
       irq_bus: irqbus0
       thread_id: 1
       other_threads: (
                       th16,
                       th18,
                       th19,
                       th20,
                       th21,
                       th22,
                       th23
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu17 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu17 TYPE swerver-spu {
       queue: th17
       thread: th17
}

OBJECT th18 TYPE niagara2 {
       mmu: stmmu18
       queue: th18
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 18))
       irq_bus: irqbus0
       thread_id: 2
       other_threads: (
                       th16,
                       th17,
                       th19,
                       th20,
                       th21,
                       th22,
                       th23
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu18 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu18 TYPE swerver-spu {
       queue: th18
       thread: th18
}

OBJECT th19 TYPE niagara2 {
       mmu: stmmu19
       queue: th19
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 19))
       irq_bus: irqbus0
       thread_id: 3
       other_threads: (
                       th16,
                       th17,
                       th18,
                       th20,
                       th21,
                       th22,
                       th23
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu19 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu19 TYPE swerver-spu {
       queue: th19
       thread: th19
}

OBJECT th20 TYPE niagara2 {
       mmu: stmmu20
       queue: th20
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 20))
       irq_bus: irqbus0
       thread_id: 4
       other_threads: (
                       th16,
                       th17,
                       th18,
                       th19,
                       th21,
                       th22,
                       th23
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu20 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu20 TYPE swerver-spu {
       queue: th20
       thread: th20
}

OBJECT th21 TYPE niagara2 {
       mmu: stmmu21
       queue: th21
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 21))
       irq_bus: irqbus0
       thread_id: 5
       other_threads: (
                       th16,
                       th17,
                       th18,
                       th19,
                       th20,
                       th22,
                       th23
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu21 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu21 TYPE swerver-spu {
       queue: th21
       thread: th21
}

OBJECT th22 TYPE niagara2 {
       mmu: stmmu22
       queue: th22
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 22))
       irq_bus: irqbus0
       thread_id: 6
       other_threads: (
                       th16,
                       th17,
                       th18,
                       th19,
                       th20,
                       th21,
                       th23
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu22 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu22 TYPE swerver-spu {
       queue: th22
       thread: th22
}

OBJECT th23 TYPE niagara2 {
       mmu: stmmu23
       queue: th23
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 23))
       irq_bus: irqbus0
       thread_id: 7
       other_threads: (
                       th16,
                       th17,
                       th18,
                       th19,
                       th20,
                       th21,
                       th22
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu23 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu23 TYPE swerver-spu {
       queue: th23
       thread: th23
}


#endif

#ifdef SP3

OBJECT swvp3 TYPE swerver-processor {
       thread0: th24
       thread1: th25
       thread2: th26
       thread3: th27
       thread4: th28
       thread5: th29
       thread6: th30
       thread7: th31
       mmu:swmmu3
}

OBJECT swmmu3 TYPE swerver-proc-mmu {
}

OBJECT th24 TYPE niagara2 {
       mmu: stmmu24
       queue: th24
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 24))
       irq_bus: irqbus0
       thread_id: 0
       other_threads: (
                       th25,
                       th26,
                       th27,
                       th28,
                       th29,
                       th30,
                       th31
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu24 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu24 TYPE swerver-spu {
       queue: th24
       thread: th24
}

OBJECT th25 TYPE niagara2 {
       mmu: stmmu25
       queue: th25
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 25))
       irq_bus: irqbus0
       thread_id: 1
       other_threads: (
                       th24,
                       th26,
                       th27,
                       th28,
                       th29,
                       th30,
                       th31
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu25 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu25 TYPE swerver-spu {
       queue: th25
       thread: th25
}

OBJECT th26 TYPE niagara2 {
       mmu: stmmu26
       queue: th26
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 26))
       irq_bus: irqbus0
       thread_id: 2
       other_threads: (
                       th24,
                       th25,
                       th27,
                       th28,
                       th29,
                       th30,
                       th31
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu26 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu26 TYPE swerver-spu {
       queue: th26
       thread: th26
}

OBJECT th27 TYPE niagara2 {
       mmu: stmmu27
       queue: th27
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 27))
       irq_bus: irqbus0
       thread_id: 3
       other_threads: (
                       th24,
                       th25,
                       th26,
                       th28,
                       th29,
                       th30,
                       th31
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu27 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu27 TYPE swerver-spu {
       queue: th27
       thread: th27
}

OBJECT th28 TYPE niagara2 {
       mmu: stmmu28
       queue: th28
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 28))
       irq_bus: irqbus0
       thread_id: 4
       other_threads: (
                       th24,
                       th25,
                       th26,
                       th27,
                       th29,
                       th30,
                       th31
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu28 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu28 TYPE swerver-spu {
       queue: th28
       thread: th28
}

OBJECT th29 TYPE niagara2 {
       mmu: stmmu29
       queue: th29
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 29))
       irq_bus: irqbus0
       thread_id: 5
       other_threads: (
                       th24,
                       th25,
                       th26,
                       th27,
                       th28,
                       th30,
                       th31
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu29 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu29 TYPE swerver-spu {
       queue: th29
       thread: th29
}

OBJECT th30 TYPE niagara2 {
       mmu: stmmu30
       queue: th30
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 30))
       irq_bus: irqbus0
       thread_id: 6
       other_threads: (
                       th24,
                       th25,
                       th26,
                       th27,
                       th28,
                       th29,
                       th31
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu30 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu30 TYPE swerver-spu {
       queue: th30
       thread: th30
}

OBJECT th31 TYPE niagara2 {
       mmu: stmmu31
       queue: th31
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 31))
       irq_bus: irqbus0
       thread_id: 7
       other_threads: (
                       th24,
                       th25,
                       th26,
                       th27,
                       th28,
                       th29,
                       th30
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu31 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu31 TYPE swerver-spu {
       queue: th31
       thread: th31
}


#endif

#ifdef SP4

OBJECT swvp4 TYPE swerver-processor {
       thread0: th32
       thread1: th33
       thread2: th34
       thread3: th35
       thread4: th36
       thread5: th37
       thread6: th38
       thread7: th39
       mmu:swmmu4
}

OBJECT swmmu4 TYPE swerver-proc-mmu {
}

OBJECT th32 TYPE niagara2 {
       mmu: stmmu32
       queue: th32
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 32))
       irq_bus: irqbus0
       thread_id: 0
       other_threads: (
                       th33,
                       th34,
                       th35,
                       th36,
                       th37,
                       th38,
                       th39
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu32 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu32 TYPE swerver-spu {
       queue: th32
       thread: th32
}

OBJECT th33 TYPE niagara2 {
       mmu: stmmu33
       queue: th33
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 33))
       irq_bus: irqbus0
       thread_id: 1
       other_threads: (
                       th32,
                       th34,
                       th35,
                       th36,
                       th37,
                       th38,
                       th39
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu33 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu33 TYPE swerver-spu {
       queue: th33
       thread: th33
}

OBJECT th34 TYPE niagara2 {
       mmu: stmmu34
       queue: th34
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 34))
       irq_bus: irqbus0
       thread_id: 2
       other_threads: (
                       th32,
                       th33,
                       th35,
                       th36,
                       th37,
                       th38,
                       th39
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu34 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu34 TYPE swerver-spu {
       queue: th34
       thread: th34
}

OBJECT th35 TYPE niagara2 {
       mmu: stmmu35
       queue: th35
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 35))
       irq_bus: irqbus0
       thread_id: 3
       other_threads: (
                       th32,
                       th33,
                       th34,
                       th36,
                       th37,
                       th38,
                       th39
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu35 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu35 TYPE swerver-spu {
       queue: th35
       thread: th35
}

OBJECT th36 TYPE niagara2 {
       mmu: stmmu36
       queue: th36
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 36))
       irq_bus: irqbus0
       thread_id: 4
       other_threads: (
                       th32,
                       th33,
                       th34,
                       th35,
                       th37,
                       th38,
                       th39
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu36 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu36 TYPE swerver-spu {
       queue: th36
       thread: th36
}

OBJECT th37 TYPE niagara2 {
       mmu: stmmu37
       queue: th37
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 37))
       irq_bus: irqbus0
       thread_id: 5
       other_threads: (
                       th32,
                       th33,
                       th34,
                       th35,
                       th36,
                       th38,
                       th39
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu37 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu37 TYPE swerver-spu {
       queue: th37
       thread: th37
}

OBJECT th38 TYPE niagara2 {
       mmu: stmmu38
       queue: th38
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 38))
       irq_bus: irqbus0
       thread_id: 6
       other_threads: (
                       th32,
                       th33,
                       th34,
                       th35,
                       th36,
                       th37,
                       th39
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu38 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu38 TYPE swerver-spu {
       queue: th38
       thread: th38
}

OBJECT th39 TYPE niagara2 {
       mmu: stmmu39
       queue: th39
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 39))
       irq_bus: irqbus0
       thread_id: 7
       other_threads: (
                       th32,
                       th33,
                       th34,
                       th35,
                       th36,
                       th37,
                       th38
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu39 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu39 TYPE swerver-spu {
       queue: th39
       thread: th39
}


#endif

#ifdef SP5

OBJECT swvp5 TYPE swerver-processor {
       thread0: th40
       thread1: th41
       thread2: th42
       thread3: th43
       thread4: th44
       thread5: th45
       thread6: th46
       thread7: th47
       mmu:swmmu5
}

OBJECT swmmu5 TYPE swerver-proc-mmu {
}

OBJECT th40 TYPE niagara2 {
       mmu: stmmu40
       queue: th40
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 40))
       irq_bus: irqbus0
       thread_id: 0
       other_threads: (
                       th41,
                       th42,
                       th43,
                       th44,
                       th45,
                       th46,
                       th47
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu40 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu40 TYPE swerver-spu {
       queue: th40
       thread: th40
}

OBJECT th41 TYPE niagara2 {
       mmu: stmmu41
       queue: th41
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 41))
       irq_bus: irqbus0
       thread_id: 1
       other_threads: (
                       th40,
                       th42,
                       th43,
                       th44,
                       th45,
                       th46,
                       th47
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu41 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu41 TYPE swerver-spu {
       queue: th41
       thread: th41
}

OBJECT th42 TYPE niagara2 {
       mmu: stmmu42
       queue: th42
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 42))
       irq_bus: irqbus0
       thread_id: 2
       other_threads: (
                       th40,
                       th41,
                       th43,
                       th44,
                       th45,
                       th46,
                       th47
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu42 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu42 TYPE swerver-spu {
       queue: th42
       thread: th42
}

OBJECT th43 TYPE niagara2 {
       mmu: stmmu43
       queue: th43
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 43))
       irq_bus: irqbus0
       thread_id: 3
       other_threads: (
                       th40,
                       th41,
                       th42,
                       th44,
                       th45,
                       th46,
                       th47
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu43 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu43 TYPE swerver-spu {
       queue: th43
       thread: th43
}

OBJECT th44 TYPE niagara2 {
       mmu: stmmu44
       queue: th44
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 44))
       irq_bus: irqbus0
       thread_id: 4
       other_threads: (
                       th40,
                       th41,
                       th42,
                       th43,
                       th45,
                       th46,
                       th47
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu44 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu44 TYPE swerver-spu {
       queue: th44
       thread: th44
}

OBJECT th45 TYPE niagara2 {
       mmu: stmmu45
       queue: th45
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 45))
       irq_bus: irqbus0
       thread_id: 5
       other_threads: (
                       th40,
                       th41,
                       th42,
                       th43,
                       th44,
                       th46,
                       th47
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu45 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu45 TYPE swerver-spu {
       queue: th45
       thread: th45
}

OBJECT th46 TYPE niagara2 {
       mmu: stmmu46
       queue: th46
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 46))
       irq_bus: irqbus0
       thread_id: 6
       other_threads: (
                       th40,
                       th41,
                       th42,
                       th43,
                       th44,
                       th45,
                       th47
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu46 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu46 TYPE swerver-spu {
       queue: th46
       thread: th46
}

OBJECT th47 TYPE niagara2 {
       mmu: stmmu47
       queue: th47
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 47))
       irq_bus: irqbus0
       thread_id: 7
       other_threads: (
                       th40,
                       th41,
                       th42,
                       th43,
                       th44,
                       th45,
                       th46
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu47 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu47 TYPE swerver-spu {
       queue: th47
       thread: th47
}


#endif

#ifdef SP6

OBJECT swvp6 TYPE swerver-processor {
       thread0: th48
       thread1: th49
       thread2: th50
       thread3: th51
       thread4: th52
       thread5: th53
       thread6: th54
       thread7: th55
       mmu:swmmu6
}

OBJECT swmmu6 TYPE swerver-proc-mmu {
}

OBJECT th48 TYPE niagara2 {
       mmu: stmmu48
       queue: th48
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 48))
       irq_bus: irqbus0
       thread_id: 0
       other_threads: (
                       th49,
                       th50,
                       th51,
                       th52,
                       th53,
                       th54,
                       th55
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu48 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu48 TYPE swerver-spu {
       queue: th48
       thread: th48
}

OBJECT th49 TYPE niagara2 {
       mmu: stmmu49
       queue: th49
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 49))
       irq_bus: irqbus0
       thread_id: 1
       other_threads: (
                       th48,
                       th50,
                       th51,
                       th52,
                       th53,
                       th54,
                       th55
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu49 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu49 TYPE swerver-spu {
       queue: th49
       thread: th49
}

OBJECT th50 TYPE niagara2 {
       mmu: stmmu50
       queue: th50
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 50))
       irq_bus: irqbus0
       thread_id: 2
       other_threads: (
                       th48,
                       th49,
                       th51,
                       th52,
                       th53,
                       th54,
                       th55
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu50 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu50 TYPE swerver-spu {
       queue: th50
       thread: th50
}

OBJECT th51 TYPE niagara2 {
       mmu: stmmu51
       queue: th51
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 51))
       irq_bus: irqbus0
       thread_id: 3
       other_threads: (
                       th48,
                       th49,
                       th50,
                       th52,
                       th53,
                       th54,
                       th55
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu51 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu51 TYPE swerver-spu {
       queue: th51
       thread: th51
}

OBJECT th52 TYPE niagara2 {
       mmu: stmmu52
       queue: th52
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 52))
       irq_bus: irqbus0
       thread_id: 4
       other_threads: (
                       th48,
                       th49,
                       th50,
                       th51,
                       th53,
                       th54,
                       th55
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu52 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu52 TYPE swerver-spu {
       queue: th52
       thread: th52
}

OBJECT th53 TYPE niagara2 {
       mmu: stmmu53
       queue: th53
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 53))
       irq_bus: irqbus0
       thread_id: 5
       other_threads: (
                       th48,
                       th49,
                       th50,
                       th51,
                       th52,
                       th54,
                       th55
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu53 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu53 TYPE swerver-spu {
       queue: th53
       thread: th53
}

OBJECT th54 TYPE niagara2 {
       mmu: stmmu54
       queue: th54
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 54))
       irq_bus: irqbus0
       thread_id: 6
       other_threads: (
                       th48,
                       th49,
                       th50,
                       th51,
                       th52,
                       th53,
                       th55
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu54 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu54 TYPE swerver-spu {
       queue: th54
       thread: th54
}

OBJECT th55 TYPE niagara2 {
       mmu: stmmu55
       queue: th55
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 55))
       irq_bus: irqbus0
       thread_id: 7
       other_threads: (
                       th48,
                       th49,
                       th50,
                       th51,
                       th52,
                       th53,
                       th54
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu55 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu55 TYPE swerver-spu {
       queue: th55
       thread: th55
}


#endif

#ifdef SP7

OBJECT swvp7 TYPE swerver-processor {
       thread0: th56
       thread1: th57
       thread2: th58
       thread3: th59
       thread4: th60
       thread5: th61
       thread6: th62
       thread7: th63
       mmu:swmmu7
}

OBJECT swmmu7 TYPE swerver-proc-mmu {
}

OBJECT th56 TYPE niagara2 {
       mmu: stmmu56
       queue: th56
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 56))
       irq_bus: irqbus0
       thread_id: 0
       other_threads: (
                       th57,
                       th58,
                       th59,
                       th60,
                       th61,
                       th62,
                       th63
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu56 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu56 TYPE swerver-spu {
       queue: th56
       thread: th56
}

OBJECT th57 TYPE niagara2 {
       mmu: stmmu57
       queue: th57
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 57))
       irq_bus: irqbus0
       thread_id: 1
       other_threads: (
                       th56,
                       th58,
                       th59,
                       th60,
                       th61,
                       th62,
                       th63
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu57 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu57 TYPE swerver-spu {
       queue: th57
       thread: th57
}

OBJECT th58 TYPE niagara2 {
       mmu: stmmu58
       queue: th58
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 58))
       irq_bus: irqbus0
       thread_id: 2
       other_threads: (
                       th56,
                       th57,
                       th59,
                       th60,
                       th61,
                       th62,
                       th63
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu58 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu58 TYPE swerver-spu {
       queue: th58
       thread: th58
}

OBJECT th59 TYPE niagara2 {
       mmu: stmmu59
       queue: th59
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 59))
       irq_bus: irqbus0
       thread_id: 3
       other_threads: (
                       th56,
                       th57,
                       th58,
                       th60,
                       th61,
                       th62,
                       th63
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu59 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu59 TYPE swerver-spu {
       queue: th59
       thread: th59
}

OBJECT th60 TYPE niagara2 {
       mmu: stmmu60
       queue: th60
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 60))
       irq_bus: irqbus0
       thread_id: 4
       other_threads: (
                       th56,
                       th57,
                       th58,
                       th59,
                       th61,
                       th62,
                       th63
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu60 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu60 TYPE swerver-spu {
       queue: th60
       thread: th60
}

OBJECT th61 TYPE niagara2 {
       mmu: stmmu61
       queue: th61
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 61))
       irq_bus: irqbus0
       thread_id: 5
       other_threads: (
                       th56,
                       th57,
                       th58,
                       th59,
                       th60,
                       th62,
                       th63
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu61 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu61 TYPE swerver-spu {
       queue: th61
       thread: th61
}

OBJECT th62 TYPE niagara2 {
       mmu: stmmu62
       queue: th62
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 62))
       irq_bus: irqbus0
       thread_id: 6
       other_threads: (
                       th56,
                       th57,
                       th58,
                       th59,
                       th60,
                       th61,
                       th63
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu62 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu62 TYPE swerver-spu {
       queue: th62
       thread: th62
}

OBJECT th63 TYPE niagara2 {
       mmu: stmmu63
       queue: th63
       freq_mhz: 800
       max-trap-levels: 6
       va_bits: 48
       physical_memory: phys_mem0
       control_registers: (("mid", 63))
       irq_bus: irqbus0
       thread_id: 7
       other_threads: (
                       th56,
                       th57,
                       th58,
                       th59,
                       th60,
                       th61,
                       th62
                      )
#if defined(RTL) || defined(PLI_REPLAY)
       extra_irq_enable: 0
#endif
}

OBJECT stmmu63 TYPE swerver-thread-mmu {
       full-swerver-decode: 1
       niagara-mmu: 1
       disable-sun4u-interrupts: 1
       model-real-sfar: 1
}

OBJECT spu63 TYPE swerver-spu {
       queue: th63
       thread: th63
}


#endif

OBJECT phys_mem0 TYPE memory-space {
       map: (
             (0x00000000000, memory_cache, 0x0, 0, 0x2000000000),
#ifdef CIOP0
             (0x0d500000000, ciop0, 0, 0, 0xb00000000),
             (0x0d300000000, bsc0, 0, 0, 0x200000000),
             (0x0c500000000, egress0, 0, 0, 0x200000000),
             (0x0c300000000, ingress0, 0, 0, 0x200000000),
             (0x0d000000000, rdma0, 0, 0, 0x300000000),
             (0x0ef00000000, echo0, 0, 0, 0x100000000),
#else
             (0x08000000000, memory_ciop, 0x0, 0, 0x7f00000000),
#endif
             (0x0ff00000000, memory0, 0x0, 0, 0x100000000))
#if defined(MOM)
       timing_model: mom0
       snoop_device: mom0
#elif !defined(NOLDST_SYNC) || defined(INDRA_MEM)
       timing_model: swvmem0
       snoop_device: swvmem0
#endif
}

OBJECT memory0 TYPE ram {
       image: memory0_image
}

OBJECT memory0_image TYPE image {
       size: 0x100000000
       queue: th00
}

OBJECT memory_cache TYPE ram {
       image: memory_cache_image
}

OBJECT memory_cache_image TYPE image {
       size: 0x2000000000
       queue: th00
}