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* OpenSPARC T2 Processor File: n2_err_adv_mcu_CRC_MULTI_ECC.s
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* ========== Copyright Header End ============================================
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO
#define L2_ERR_STAT_REG 0xAB00000000
#define L2_ERR_ADDR_REG 0xAC00000000
#define TEST_DATA1 0x1000100081c3e008
#define TEST_DATA2 0x2000200081c3e008
#define L2_ES_W1C_VALUE 0xc03ffff800000000
#define DRAM_ES_W1C_VALUE 0xfe00000000000000
#define DRAM_ERR_INJ_REG 0x8400000290
#define DRAM_ERR_STAT_REG 0x8400000280
#define ERROR_ADDR 0x20200000
#define DRAM_SCRUB_FREQ_REG 0x8400000018
#define DRAM_SCRUB_ENB_REG 0x8400000040
ldxa [%g0] ASI_LSU_CONTROL, %l0
! Remove the lower 2 bits (I-Cache and D-Cache enables)
stxa %l0, [%g0] ASI_LSU_CONTROL
setx DRAM_ES_W1C_VALUE, %l0, %g2
setx 0x8400000280, %l1, %g6
setx L2_ES_W1C_VALUE, %l0, %g4
setx 0xbb00000000, %l1, %g7
set_DRAM_error_inject_mcu0:
!sllx %l2, DRAM_EI_SSHOT, %l2
setx 0x8400000290, %l0, %g4
set_L2_Direct_Mapped_Mode:
setx 0xa900000000, %l0, %g1
setx 0x0123456789abcdef, %l1, %g2
brnz %l3,st_to_L2_way0_and_MCU0
ld_from_error_and_nonerror_address:
brnz %l2,ld_from_error_and_nonerror_address
ld_from_L2_bank0_for_CRC:
brnz %g3,ld_from_L2_bank0_for_CRC
setx 0x8400000288, %l6, %g5
setx 0xbc00000000, %l6, %g5
setx 0xbc00000040, %l6, %g5
/*******************************************************
*******************************************************/