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* OpenSPARC T2 Processor File: n2_err_l2_LVC_8core.s
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#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define MAIN_PAGE_HV_ALSO
#define L2_ENTRY_PA 0x517590000
#define TEST_DATA 0x555555555555555
#define L2_ES_W1C_VALUE 0xc03ffff800000000
#define L2_ESR_MASK 0xfffffffff0000000
#define SYNC_ADDR 0x55500000
.global My_Corrected_ECC_error_trap
! Boot code does not provide TLB translation for IO address space
ba main_all_other_threads
! Now access L2 control and status registers
setx 0x1111111111111111, %g7, %g2
setx 0x44400000, %l0, %g1
setx 0x3ffc0, %l0, %g2 ! Mask for extracting [17:6]
! With each iteration ERROR_STEERING value goes from 0, 1, 2, ...63
! Dont read the register value
set_L2_Directly_Mapped_Mode_errorsteer:
mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode
sllx %i3, 15, %o4 ! %i3 has the thread id = 0, 1, 2,3, ...63 ;
! to write as core-steering thread
setx 0x5555555555555555, %g7, %g4
! Generate L2 VD Diag read address
! Addressing: [39:32] See PRM, [22] 1 for V/D, [17:8] set, [8:6] bank, [2:0] = 0
sllx %g4, 32, %g6 ! Bits [39:32]
sllx %g4, 22, %g5 ! Bit [22]
ldx [%g6], %g4 !Diagnostic access
sllx %g5, %i4, %g7 ! %i3=1,2,3,....16
xor %g4, %g7, %g5 ! inject single bit error
setx 0xaaaaaaaa, %g7, %g5
sllx %i3, 24, %g6 ! %i3=1,2,3,....16
! to have different tag; same index
or %g1, %g6, %g3 ! %g1 had the PA
nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
! Each Thread will Write its THID to SYNC_ADDR
ldx [%o2], %o3 ! Each thread will write to SYNC_ADDR its THID in trap handler
cmp %o3, %i3 ! %i3 has the THID which will get the Trap
bne %xcc, wait_for_trap_loop
add %g1, %g4, %g1 ! to go to the next Set; <17:9>
clr %i4 ! reset %i4 when goes to 38
!trap handler increases %i0
check_err_trap_taken_th0:
/************************ NON-ZERO THREADS ***********************************/
! timeout for TH1=0x400, TH2=0x800
wait_for_err_trap_all_th:
!trap handler increases %i0
bne wait_for_err_trap_all_th
/*******************************************************
*******************************************************/
My_Corrected_ECC_error_trap:
setx L2_ESR_MASK, %g7, %g3
setx LVC_MASK_ZERO, %g7, %g2
and %g1, %g2, %g2 ! %g1 has esr value
cmp %g2, %g0 ! makes sure <27:14>, <6:0> are 0 for VD
! makes sure <27:14>, <13:7> are 0 for UA
setx LVC_MASK_NONZERO, %g7, %g2
and %g1, %g2, %g2 ! %g1 has esr value
cmp %g2, %g0 ! makes sure <13:7> nonzero for VD
! makes sure <6:0> nonzero for UA
setx 0xc03ffffc00000000, %g7, %g2
setx 0xff00000000000000, %g7, %g2
setx 0x8900000000000000, %g7, %g4