verif/diag/assembly/arch/error/vec/n2_ras_vec_mcu_dsu_trap.s

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: n2_ras_vec_mcu_dsu_trap.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* otherwise unspecified.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
*
* ========== Copyright Header End ============================================
*/
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO


#define  TEST_DATA1         0x2000200081c3e008

#ifdef MCU0
#define L2_BANK_ADDR        0x0
#define MCU_BANK_ADDR       0x0
#define  DRAM_ERR_INJ_REG   0x8400000290
#define  DRAM_ERR_STAT_REG  0x8400000280
#define  DRAM_ERR_ADDR_REG  0x8400000288
#define  DRAM_SCRB_FREQ_REG 0x8400000018
#define  DRAM_SCRB_ENB_REG  0x8400000040
#define  L2_ERR_STAT_REG    0xAB00000000
#endif

#ifdef MCU1
#define L2_BANK_ADDR        0x80
#define MCU_BANK_ADDR       0x80
#define  DRAM_ERR_INJ_REG   0x8400001290
#define  DRAM_ERR_STAT_REG  0x8400001280
#define  DRAM_ERR_ADDR_REG  0x8400001288
#define  DRAM_SCRB_FREQ_REG 0x8400001018
#define  DRAM_SCRB_ENB_REG  0x8400001040
#define  L2_ERR_STAT_REG    0xAB00000080
#endif

#ifdef MCU2
#define L2_BANK_ADDR        0x100
#define MCU_BANK_ADDR       0x100
#define  DRAM_ERR_INJ_REG   0x8400002290
#define  DRAM_ERR_STAT_REG  0x8400002280
#define  DRAM_ERR_ADDR_REG  0x8400002288
#define  DRAM_SCRB_FREQ_REG 0x8400002018
#define  DRAM_SCRB_ENB_REG  0x8400002040
#define  L2_ERR_STAT_REG    0xAB00000100
#endif

#ifdef MCU3
#define L2_BANK_ADDR        0x180
#define MCU_BANK_ADDR       0x180
#define  DRAM_ERR_INJ_REG   0x8400003290
#define  DRAM_ERR_STAT_REG  0x8400003280
#define  DRAM_ERR_ADDR_REG  0x8400003288
#define  DRAM_SCRB_FREQ_REG 0x8400003018
#define  DRAM_SCRB_ENB_REG  0x8400003040
#define  L2_ERR_STAT_REG    0xAB00000180
#endif


#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"


.text
.global  main
.global  My_Recoverable_Sw_error_trap


main:
  ta T_CHANGE_HPRIV
  clr   %o0
  clr   %o1

disable_l1:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove the lower 2 bits (I-Cache and D-Cache enables)
  andn  %l0, 0x3, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL

set_DRAM_scrub_frequency:
  setx  DRAM_SCRB_FREQ_REG, %l0, %l1
  mov   0x1, %l0
  stx   %l0, [%l1]
  membar #Sync


enable_err_reporting:
  setx L2EE_PA0, %l0, %l1
  add   %l1, L2_BANK_ADDR, %l1
  ldx   [%l1], %l2
  mov   0x3, %l0
  or    %l2, %l0, %l2
  stx   %l2, [%l1]
  membar #Sync

set_DRAM_error_inject_ch0:
  set   0x606, %l1                ! ECC Mask (1-bit error)
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_SSHOT, %l3
  Or    %l1, %l3, %l1           ! Set single shot ;
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_ENB, %l3
  or    %l1, %l3, %l1           ! Enable error injection for the next write
  setx  DRAM_ERR_INJ_REG, %l3, %g6
!  add   %g6, MCU_BANK_ADDR, %g6
  stx   %l1, [%g6]
  membar 0x40

store_to_L2:
  setx  TEST_DATA1, %l0, %g5


set_L2_Directly_Mapped_Mode_errorsteer:
        setx    L2CS_PA0, %l6, %g1
        add     %g1, L2_BANK_ADDR, %g1
        ldx     [%g1], %o6

        mov     0x2, %o5                ! L2_CSR_REG<1>=1 => DM mode

        ldxa    [%g0]ASI_INTR_ID, %o4   ! get the thread id; for core-portable
        sllx    %o4, 15, %o4            ! L2_CSR_REG<21:15> = ERROR_STEER

        or      %o5, %o4, %o5

        or      %o6, %o5, %o6

        stx     %o6, [%g1]
        membar  0x40


store_to_L2_way0:
  setx  0x002000, %l0, %g2  ! bits [21:18] select way
  add   %g2, L2_BANK_ADDR, %g2
  stx %g5, [%g2]
  stx %g5, [%g2+8]
  membar #Sync

! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_0:
  setx  0x21002000, %l0, %g3 ! bits [21:18] select way
  add   %g3, L2_BANK_ADDR, %g3
  stx %g5, [%g3]
!  stx %g5, [%g3+8]
  membar #Sync

enable_DRAM_scrub:
  setx  DRAM_SCRB_ENB_REG, %l0, %l1
  mov   0x1, %l0
  stx   %l0, [%l1]
  membar #Sync

        setx    0x22002000, %l0, %g3 ! bits [21:18] select way
        add     %g3, L2_BANK_ADDR, %g3  ! 01/07/07: cause fill from the appropreate mcu
        clr     %i5
Nops:
        cmp     %o0, %g0
        bne     %xcc, check_error_trap
        nop

        ldx     [%g3], %g1 ! cause  a fill
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop

        add     %g3, 0x200, %g3
        inc     %i5
        cmp     %i5, 0x200
        bne     Nops
        nop


check_error_trap:
 setx   EXECUTED, %l1, %l0
  cmp   %o0, %l0
  bne   test_fail
  nop

  ba    test_pass
  nop


        /**************** Trap Handler *******************/
My_Recoverable_Sw_error_trap:
  ! Signal trap taken
  setx  EXECUTED, %l0, %o0
  ! save trap type value
  rdpr  %tt, %o1

check_l2esr:
        setx    L2_ERR_STAT_REG, %g7, %g1
        ldx   [%g1], %g2

        setx    0x2000000000, %g7, %g3          !DSU
        cmp     %g2, %g3
        bne     %xcc, test_fail
        nop

check_mcuesr:
        setx    DRAM_ERR_STAT_REG, %g7, %g1
        ldx     [%g1], %g2

        setx    0x0400000000000606, %g7, %g3    !SYND =0x606; DSU
        cmp     %g2, %g3
        bne     %xcc, test_fail
        nop

check_DSFSR:
        set     0x18, %g3
        ldxa    [%g3] 0x58, %g2
        cmp     %g0, %g2
        bne     test_fail
        nop

check_DESR:
        ldxa    [%g0] 0x4c, %g2
        setx    0xb000000000000000, %g7, %g3              ! <63>=f=1; <61>=S=1; 60:56=10000
        cmp     %g2, %g3
        bne     %xcc, test_fail
        nop

check_mcu_EAR:
!       setx    0x8400000288, %l1, %g1
        setx    DRAM_ERR_ADDR_REG, %g7, %g1
        ldx     [%g1], %g2
        setx    0x2000, %l1, %g3
        cmp     %g2, %g3
!       bne     %xcc, test_fail
        nop

        done
        nop

  ba    test_pass
  nop

/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP


test_fail:
ta  T_BAD_TRAP